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公开(公告)号：US4635231A
公开(公告)日：1987-01-06
申请号：US662900
申请日：1984-10-19
IPC分类号： G11C7/10 , G11C11/411 , G11C11/416 , G11C11/40
CPC分类号： G11C11/4116 , G11C11/416 , G11C7/1024
摘要： To extend the function of a bipolar type RAM, a register function is added to the RAM function. The register function is such that the contents stored in a memory cell is inputted to a differential switch, and the output to the differential switch is derived out to constantly read out the stored content of a desired bit with a simple circuit construction.
摘要翻译： 为了扩展双极型RAM的功能，将寄存器功能添加到RAM功能。 寄存器功能使得存储在存储单元中的内容被输入到差分开关，并且导出差分开关的输出，以通过简单的电路结构不断地读出存储的所需位的内容。
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公开(公告)号：US4635292A
公开(公告)日：1987-01-06
申请号：US682321
申请日：1984-12-17
CPC分类号： G06T5/20
摘要： This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.
摘要翻译： 本发明提供并行部分图像处理，例如使用可以容易地形成为大规模集成电路并可用于各种目的的图像处理器的空间卷积或非线性相邻算术运算。 图像处理器具有加法器 - 减法器，乘法器，互易数存储器，其中地址的倒数和移位量存储在每个地址处，以及移位寄存器。 因此，处理器能够通过将乘数乘以乘法器的倒数并通过移位乘法结果来进行高速分频操作。 此外，通过在程序控制下将输入切换到加法器 - 减法器和乘法器，可以对存储在部分图像存储器中的m行和n列的部分图像数据执行任意加法，减法，乘法和除法 图像处理器。
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公开(公告)号：US4791677A
公开(公告)日：1988-12-13
申请号：US941625
申请日：1986-12-11
IPC分类号： G06T5/20 , G06K9/36 , G06F15/336 , G06K9/64
CPC分类号： G06T5/20
摘要： An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.
摘要翻译： 一种图像信号处理器，包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m行x1列像素的扩展使用寄存器。 因此，可以容易地进行局部图像区域的扩展和并行处理。
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公开(公告)号：US4845767A
公开(公告)日：1989-07-04
申请号：US266893
申请日：1988-11-03
IPC分类号： G06T5/20
CPC分类号： G06T5/20
摘要： An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.1 column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.
摘要翻译： 一种图像信号处理器，其包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m row×1列像素的扩展使用寄存器。 因此，可以容易地进行局部图像区域的扩展和并行处理。
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5.发明授权Digital processor capable of concurrently executing external memory access and internal instructions 失效能够同时执行外部存储器访问和内部指令的数字处理器
公开(公告)号：US5499348A
公开(公告)日：1996-03-12
申请号：US266104
申请日：1994-06-27
申请人： Toshiyuki Araki , Kunitoshi Aono , Masaki Toyokura
发明人： Toshiyuki Araki , Kunitoshi Aono , Masaki Toyokura
IPC分类号： G06F9/38
CPC分类号： G06F9/3824
摘要： The digital processor includes an instruction memory, a sequencer, a decoder, and a memory reference control circuit. In case the sequencer reads the external memory reference instruction, the memory reference control circuit serves to fetch an external memory reference instruction signal and an operand of the external memory reference signal delivered from the decoder, hold the operand until the external memory cycle executed by the external memory reference instruction is terminated, and release the operand when the cycle is terminated. The sequencer serves to have succeeding instructions read out continuously while the external memory reference instruction is being executed, and to concurrently execute the read-out instructions when the read-out instructions refer to resources not occupied by the external memory reference instruction, so as to execute the read-out instructions in parallel with the external memory reference instruction, thereby improving the throughput of the total processing.
摘要翻译： 数字处理器包括指令存储器，定序器，解码器和存储器参考控制电路。 在定序器读取外部存储器参考指令的情况下，存储器参考控制电路用于获取从解码器传送的外部存储器参考指令信号和外部存储器参考信号的操作数，保持操作数直到由 外部存储器参考指令终止，并且在循环终止时释放操作数。 当执行外部存储器参考指令时，定序器用于连续地读出后续指令，并且当读出指令参考未被外部存储器参考指令占用的资源时，同时执行读出指令，以便 执行与外部存储器参考指令并行的读出指令，从而提高总处理的吞吐量。
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公开(公告)号：US6026486A
公开(公告)日：2000-02-15
申请号：US859308
申请日：1997-05-20
申请人： Hisashi Kodama , Kunitoshi Aono
发明人： Hisashi Kodama , Kunitoshi Aono
CPC分类号： G06F9/3822 , G06F9/30076 , G06F9/30149 , G06F9/30174 , G06F9/30178 , G06F9/30189 , G06F9/3802 , G06F9/3836 , G06F9/3855 , G06F9/3885
摘要： A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit processor. If the received instruction is analyzed to be a 32-bit processor instruction, the control unit controls the 32-bit processor with the aid of two 16-bit instruction control units. If the received instruction is a 16-bit processor instruction, the 32-bit processor control unit sends a 16-bit processor mode signal to each of the 16-bit instruction control units. One of the two 16-bit instruction control units controls one of two 16-bit processors which are divisions of the 32-bit processor while the other 16-bit instruction control unit controls the other 16-bit processor. The present invention makes it possible to have a single, wide bitwidth processor serve as a plurality of narrow bitwidth processors depending upon the type of processing. Various operations can be performed in parallel, thereby improving processor performance.
摘要翻译： 32位处理器控制单元从存储器接收指令。 然后，控制单元确定接收到的指令是针对32位处理器还是针对16位处理器。 如果接收到的指令被分析为32位处理器指令，则控制单元借助于两个16位指令控制单元控制32位处理器。 如果接收到的指令是16位处理器指令，则32位处理器控制单元向16位指令控制单元中的每一个发送16位处理器模式信号。 两个16位指令控制单元之一控制两个16位处理器中的一个，它们是32位处理器的分区，而另一个16位指令控制单元控制另一个16位处理器。 本发明使得可以根据处理的类型使单个宽的位宽处理器用作多个窄位宽处理器。 可以并行执行各种操作，从而提高处理器的性能。
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7.发明授权Program control type vector processor for executing a vector pipeline operation for a series of vector data which is in accordance with a vector pipeline 失效程序控制类型向量处理器，用于对与矢量流水线相对应的一系列向量数据执行向量流水线操作
公开(公告)号：US5299320A
公开(公告)日：1994-03-29
申请号：US752787
申请日：1991-08-30
申请人： Kunitoshi Aono , Masaki Toyokura , Toshiyuki Araki , Akihiko Ohtani , Hisashi Kodama , Kiyoshi Okamoto
发明人： Kunitoshi Aono , Masaki Toyokura , Toshiyuki Araki , Akihiko Ohtani , Hisashi Kodama , Kiyoshi Okamoto
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/345 , G06F9/3885
摘要： In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.
摘要翻译： 在用于执行包括包括用于执行流水线操作的数据处理器的向量流水线指令的多个指令的程序控制类型处理器中，提供了一种程序控制器，其包括程序存储器，程序计数器和解码器，并且还提供有地址生成器 和数据存储器。 当从程序存储器中读出向量流水线指令并由解码器解码时，程序控制器停止程序计数器并输出起始信号，然后根据向量管线的内容来控制数据处理器的操作 指令。 数据处理器通过由程序控制器控制从数据存储器输出的数据执行流水线操作，并且程序控制器在接收到结束之后响应于向量流水线指令检测预定数量的循环执行的流水线操作的完成 信号，然后依次执行向量流水线指令之后的指令。
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公开(公告)号：US20100321982A1
公开(公告)日：2010-12-23
申请号：US12867392
申请日：2009-12-16
CPC分类号： H01L27/101 , G11C13/0002 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).
摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。
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公开(公告)号：US5293596A
公开(公告)日：1994-03-08
申请号：US658154
申请日：1991-02-20
申请人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
发明人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
CPC分类号： G06F12/0207
摘要： A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.
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公开(公告)号：US08125817B2
公开(公告)日：2012-02-28
申请号：US12867392
申请日：2009-12-16
CPC分类号： H01L27/101 , G11C13/0002 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).
摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。
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