公开(公告)号：US08938586B2

公开(公告)日：2015-01-20

申请号：US12529228

申请日：2009-02-10

申请人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Ryoichi Kato

发明人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Ryoichi Kato

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F2212/7207

摘要： A memory system includes: a cache memory, a nonvolatile semiconductor memory, and a controller. The controller includes a plurality of management tables that manage data stored in the cache memory and the nonvolatile semiconductor memory using a cluster unit and a track unit. The controller performs data flushing processing from the cache memory to the nonvolatile semiconductor memory when the number of track units registered in the cache memory exceeds a predetermined threshold. Data may be flushed to the nonvolatile memory in different size data units such as a cluster or a track. Data flushing processing may also be performed if a last free way is used when data writing processing is performed on the cache memory managed in a set associative system. The nonvolatile semiconductor memory can be a NAND flash memory.

摘要翻译： 存储器系统包括：高速缓冲存储器，非易失性半导体存储器和控制器。 控制器包括多个管理表，其管理存储在高速缓冲存储器中的数据和使用集群单元和轨道单元的非易失性半导体存储器。 当登记在高速缓冲存储器中的轨道单元的数量超过预定阈值时，控制器执行从高速缓冲存储器到非易失性半导体存储器的数据刷新处理。 可以将数据刷新到不同大小的数据单元（例如，群集或轨道）中的非易失性存储器。 如果在对集合关联系统中管理的高速缓冲存储器上执行数据写入处理时，如果使用最后的自由方式，则也可以执行数据刷新处理。 非易失性半导体存储器可以是NAND闪存。

公开(公告)号：US08601219B2

公开(公告)日：2013-12-03

申请号：US12402994

申请日：2009-03-12

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C2211/5641

摘要： A memory system includes a first storing area included in a volatile semiconductor memory, a second and a third storing area included in a nonvolatile semiconductor memory, a controller that allocates the storage area of the nonvolatile semiconductor memory to the second storing area and the third storing area in a logical block unit associated with one or more blocks. The second storing area is configured to be managed with a first management unit. The third storing area is configured to be managed with a second management unit, a size of the second management unit being larger than a size of the first management unit. When flushing of data from the first storing area to the second storing area or the third storing area is determined, the controller collects, from at least one of the first storing area, the second storing area and the third storing area, data other than the data determined to be flushed and controls the flushing of the data such that a total of the data is a natural number times as large as the block unit as much as possible.

摘要翻译： 一种存储系统，包括易失性半导体存储器中包括的第一存储区域，包括在非易失性半导体存储器中的第二和第三存储区域，将非易失性半导体存储器的存储区域分配给第二存储区域和第三存储区域的控制器 与一个或多个块相关联的逻辑块单元中的区域。 第二存储区域被配置为由第一管理单元管理。 第三存储区域被配置为由第二管理单元管理，第二管理单元的大小大于第一管理单元的大小。 当从第一存储区域向第二存储区域或第三存储区域清空数据时，控制器从第一存储区域，第二存储区域和第三存储区域中的至少一个收集除了 确定要刷新的数据并且控制数据的刷新，使得数据的总和是尽可能多的与块单元一样大的自然数。

公开(公告)号：US08438343B2

公开(公告)日：2013-05-07

申请号：US12529227

申请日：2009-02-10

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Shigehiro Asano ,  Shinichi Kanno ,  Toshikatsu Hida

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Shigehiro Asano ,  Shinichi Kanno ,  Toshikatsu Hida

IPC分类号： G06F12/06

CPC分类号： G06F11/1451 ,  G06F11/1471 ,  G06F12/0246 ,  G06F12/06 ,  G06F2212/7207 ,  G11C7/20 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/105

摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.

公开(公告)号：US08225047B2

公开(公告)日：2012-07-17

申请号：US12394692

申请日：2009-02-27

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/00

CPC分类号： G06F12/0868 ,  G06F12/0862 ,  G06F2212/214

摘要： A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.

摘要翻译： 一种存储器系统，包括一个控制器，其读出写入到非易失性第二存储区域中的数据，从该数据读出数据被写入页单元，将第一存储区域写入作为包含在半导体存储器中的高速缓冲存储器 并将数据传送到主机设备。 当从主机设备的读出请求满足预定条件时，控制器执行从读出请求指定的逻辑地址范围的终端到第一存储区数据的第一预取中的至少一个， 当前处理到在页面单元中对齐的逻辑地址的边界，以及第二预取，用于从在页面单元中对齐的逻辑地址的边界读出数据到逻辑地址的下一个边界。

公开(公告)号：US08209471B2

公开(公告)日：2012-06-26

申请号：US12529192

申请日：2009-02-10

申请人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki

发明人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7211

摘要： A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.

摘要翻译： 根据本发明的实施例的存储器系统包括：数据管理单元120被划分为DR​​AM层管理单元120a，逻辑NAND层管理单元120b和物理NAND层管理单元120c至 使用各个管理单元独立地执行DRAM层，逻辑NAND层和物理NAND层的管理，从而执行有效的块管理。

公开(公告)号：US08190812B2

公开(公告)日：2012-05-29

申请号：US12529235

申请日：2009-02-10

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/00

CPC分类号： G11C16/102 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/1471 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/105 ,  G11C29/00

摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.

摘要翻译： 存储器系统包括易失性第一存储单元，非易失性第二存储单元，其中排列可存储多值数据的多个存储器单元，存储单元具有多个页面，以及控制器，其执行数据传输 主机设备和第二存储单元。 控制器包括一个保存处理单元，其在一次写入数据被写入第二存储单元之后，当数据被写入到存储单元的低位页面中时 写入数据，低位页的数据和破损信息恢复处理单元，当低位页中的数据被破坏时，使用备份数据恢复断开的数据。

公开(公告)号：US08176237B2

公开(公告)日：2012-05-08

申请号：US12984337

申请日：2011-01-04

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/02

CPC分类号： G06F12/0804 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/7203 ,  G06F2212/7205

摘要： A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.

摘要翻译： 控制器执行用于在第一存储区域中以扇区为单位写入多个数据的第一处理; 第二处理，用于将存储在第一存储区域中的数据在第一管理单元中的第一输入缓冲器中刷新自然数倍于扇区单元的两倍或更大; 在第二管理单元中将存储在第一存储区域中的数据刷新到与第一管理单元一样大的自然数倍的两倍或更大的第二处理; 将其中将所有页面写入所述第一输入缓冲器的逻辑块重定位到所述第二存储区域的第四处理; 将其中将所有页面写入第二输入缓冲器的逻辑块重新定位到第三存储区域的第五处理; 以及第六处理，用于将存储在第二存储区域中的多个数据刷新到第二管理单元中的第二输入缓冲器。

公开(公告)号：US08108594B2

公开(公告)日：2012-01-31

申请号：US12529223

申请日：2009-02-10

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Hiroki Matsudaira

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Hiroki Matsudaira

IPC分类号： G06F12/00

CPC分类号： G06F11/1435 ,  G06F11/1441 ,  G06F11/1471 ,  G06F11/1474

摘要： To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.

摘要翻译： 提供即使在数据写入过程中发生程序错误时也可以确保还原管理信息的存储系统。 在“日志写入（1）”作为预登录之后，当执行数据写入时发生程序错误（数据写入错误）时，存储器系统再次执行数据写入，而不获取对应于数据重写的预记录 处理。 在完成数据写入之后，内存系统在不生成后记录的情况下获取快照而不是后记录，并完成处理。

公开(公告)号：US20110307667A1

公开(公告)日：2011-12-15

申请号：US12529228

申请日：2009-02-10

申请人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Ryoichi Kato

发明人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Ryoichi Kato

IPC分类号： G06F12/08

CPC分类号： G06F12/0246 ,  G06F2212/7207

摘要： A memory system according to an embodiment of the present invention comprises: a first management table that manages addresses concerning the data written in a first storing area; and a second management table that manages, in an address unit of a second management unit, information indicating temporal order of the data stored in the first storing area and manages, for each of addresses in a second management unit, number-of-valid-data information indicating a number of data in the first management unit included in the addresses in the second management unit.

摘要翻译： 根据本发明的实施例的存储器系统包括：第一管理表，其管理与第一存储区域中写入的数据有关的地址; 以及第二管理表，其在第二管理单元的地址单元中管理指示存储在第一存储区域中的数据的时间顺序的信息，并且对于第二管理单元中的每个地址管理有效 - 指示包括在第二管理单元中的地址中的第一管理单元中的数据的数量的数据信息。

公开(公告)号：US20100312948A1

公开(公告)日：2010-12-09

申请号：US12529126

申请日：2009-02-10

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0866 ,  G06F11/1068 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/7203

摘要： A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.

摘要翻译： 存储器系统包括以等于或小于簇的单位执行写入和读出的DRAM 20，以页单元执行写入和读出的NAND存储器10以及管理表组，其中管理信息包括存储位置 存储在DRAM 20和NAND存储器10中的数据被存储。 当从外部接收到读出请求时，数据管理单元120在映射了要求读出的逻辑地址区域的NAND存储器的存储区域中存在未写入的逻辑地址区域时，通知存储的固定数据 在DRAM 20中与逻辑地址区域相关联到外部。