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公开(公告)号:US12211807B2
公开(公告)日:2025-01-28
申请号:US18490866
申请日:2023-10-20
Applicant: Texas Instruments Incorporated
Inventor: Alexei Sadovnikov , Sheldon Douglas Haynie , Ujwal Radhakrishna
Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.
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公开(公告)号:US12113128B2
公开(公告)日:2024-10-08
申请号:US17330095
申请日:2021-05-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Alexei Sadovnikov , Natalia Lavrovskaya
IPC: H01L29/78 , H01L21/28 , H01L29/06 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7816 , H01L21/28123 , H01L29/0653 , H01L29/4238 , H01L29/66681 , H01L21/28052 , H01L21/28211
Abstract: An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.
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公开(公告)号:US12015057B2
公开(公告)日:2024-06-18
申请号:US17156612
申请日:2021-01-24
Applicant: Texas Instruments Incorporated
Inventor: Mahalingam Nandakumar , Alexei Sadovnikov , Henry Litzmann Edwards , Jarvis Benjamin Jacobs
IPC: H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/26 , H01L29/66
CPC classification number: H01L29/26 , H01L21/823892 , H01L27/092 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.
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公开(公告)号:US20240178318A1
公开(公告)日:2024-05-30
申请号:US18072201
申请日:2022-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Martin B. Mollat , Henry L. Edwards , Alexei Sadovnikov
IPC: H01L29/78 , H01L21/8238 , H01L29/66
CPC classification number: H01L29/7835 , H01L21/823814 , H01L29/66659 , H01L29/7816
Abstract: An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter.
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公开(公告)号:US11869986B2
公开(公告)日:2024-01-09
申请号:US17459991
申请日:2021-08-27
Applicant: Texas Instruments Incorporated
Inventor: Umamaheswari Aghoram , Akram Ali Salman , Binghua Hu , Alexei Sadovnikov
IPC: H01L29/866 , H01L27/02 , H01L29/66
CPC classification number: H01L29/866 , H01L27/0255 , H01L29/66106 , H01L27/0259
Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.
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公开(公告)号:US11830830B2
公开(公告)日:2023-11-28
申请号:US17318556
申请日:2021-05-12
Applicant: Texas Instruments Incorporated
Inventor: Alexei Sadovnikov , Sheldon Douglas Haynie , Ujwal Radhakrishna
CPC classification number: H01L23/647 , H01L29/401 , H01L29/404 , H01L29/407 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835 , H01L2223/6672
Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.
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公开(公告)号:US11791405B2
公开(公告)日:2023-10-17
申请号:US17375598
申请日:2021-07-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Alexei Sadovnikov , Natalia Lavrovskaya
IPC: H01L29/739 , H01L29/66 , H01L21/265 , H01L21/768 , H01L29/45 , H01L21/02 , H01L29/49 , H01L21/311 , H01L29/08 , H01L21/324
CPC classification number: H01L29/7393 , H01L21/02164 , H01L21/26513 , H01L21/31105 , H01L21/324 , H01L21/76889 , H01L29/0808 , H01L29/45 , H01L29/4916 , H01L29/66325
Abstract: An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.
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38.
公开(公告)号:US11588019B2
公开(公告)日:2023-02-21
申请号:US17540428
申请日:2021-12-02
Applicant: Texas Instruments Incorporated
Inventor: Alexei Sadovnikov , Natalia Lavrovskaya
IPC: H01L29/08 , H01L21/82 , H01L29/732 , H01L29/10 , H01L29/66 , H01L27/06 , H01L21/8249 , H01L21/265 , H01L21/266 , H01L29/36
Abstract: A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region.
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39.
公开(公告)号:US20220093737A1
公开(公告)日:2022-03-24
申请号:US17540428
申请日:2021-12-02
Applicant: Texas Instruments Incorporated
Inventor: Alexei Sadovnikov , Natalia Lavrovskaya
IPC: H01L29/08 , H01L29/732 , H01L29/10 , H01L29/66 , H01L27/06 , H01L21/8249 , H01L21/265 , H01L21/266 , H01L29/36
Abstract: A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region.
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公开(公告)号:US11094806B2
公开(公告)日:2021-08-17
申请号:US15859292
申请日:2017-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Alexei Sadovnikov , Natalia Lavrovskaya
IPC: H01L29/739 , H01L29/66 , H01L21/265 , H01L21/768 , H01L29/45 , H01L21/02 , H01L29/49 , H01L21/311 , H01L29/08 , H01L21/324
Abstract: A method to fabricate a transistor, the method comprising: implanting dopants in a semiconductor to form a collector region having majority carriers of a first type; implanting dopants with a first dosage and implanting dopants with a second dosage in the collector region to form a base region having majority carriers of a second type, wherein the second dosage is at a lower energy than the first dosage; forming a gate oxide on the base region; forming a gate material on the gate oxide; forming the gate material and the gate oxide to leave uncovered an emitter area of the base region; and implanting dopants in the emitter area to form an emitter region having majority carriers of the first type.
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