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公开(公告)号：US20230046592A1
公开(公告)日：2023-02-16
申请号：US17464261
申请日：2021-09-01
Applicant: Texas Instruments Incorporated
Inventor： Rajat Chauhan , Sandeep Shylaja Krishnan , Joseph Alan Sankman
Abstract: In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (RDEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (RPTAT) of the differential amplifier stage, a third resistor (R1PTAT) of the scaling amplifier stage, and a fourth resistor (R2PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.
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公开(公告)号：US11353901B2
公开(公告)日：2022-06-07
申请号：US17097988
申请日：2020-11-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Joseph Alan Sankman , Avinash Shreepathi Bhat
Abstract: An electronic circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor has a first threshold voltage. The second transistor has a second threshold voltage that is different from the first threshold voltage. The second transistor is coupled to the first transistor. The variable resistor is coupled to the first transistor and the second transistor. The variable resistor is configured to adjust a temperature coefficient of the electronic circuit. The electronic circuit is configured to generate a reference voltage based on a difference of the first threshold voltage and the second threshold voltage.
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公开(公告)号：US11177803B2
公开(公告)日：2021-11-16
申请号：US17038100
申请日：2020-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Divya Kaur , Rajat Chauhan
IPC: H03K17/22
Abstract: A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.
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公开(公告)号：US11079780B2
公开(公告)日：2021-08-03
申请号：US16677284
申请日：2019-11-07
Applicant: Texas Instruments Incorporated
Inventor： Jayateerth Pandurang Mathad , Rajat Chauhan
Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.
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公开(公告)号：US20210184671A1
公开(公告)日：2021-06-17
申请号：US17038100
申请日：2020-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Divya Kaur , Rajat Chauhan
IPC: H03K17/22
Abstract: A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.
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Patent Agency Ranking
公开(公告)号：US20200073423A1
公开(公告)日：2020-03-05
申请号：US16677284
申请日：2019-11-07
Applicant: Texas Instruments Incorporated
Inventor： Jayateerth Pandurang Mathad , Rajat Chauhan
Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.
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公开(公告)号：US20190319614A1
公开(公告)日：2019-10-17
申请号：US15952549
申请日：2018-04-13
Applicant: Texas Instruments Incorporated
Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.
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公开(公告)号：US10447142B1
公开(公告)日：2019-10-15
申请号：US16227314
申请日：2018-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Vinod Joseph Menezes , Manikandan RR , Rajat Chauhan , Vipul Kumar Singhal , Mahesh Madhukar Mehendale , Kaichien Tsai
Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.
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公开(公告)号：US10432192B1
公开(公告)日：2019-10-01
申请号：US16110892
申请日：2018-08-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Divya Kaur , Rajat Chauhan , Vipul Kumar Singhal
IPC: H03K17/22 , H03K17/14 , H03K3/3565
Abstract: A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.
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公开(公告)号：US10262722B2
公开(公告)日：2019-04-16
申请号：US15447230
申请日：2017-03-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prajkta Vyavahare , Rajat Chauhan , Siva Srinivas Kothamasu
IPC: G11C7/10 , G11C11/4093 , G11C11/4074 , H03K17/687 , G06F13/10 , G11C11/4094 , G06F1/3296
Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
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