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    Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability
    31.
    发明申请
    Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability 失效
    内存自检引擎装置和方法，具有故障触发和每种负载能力的多种模式

    公开(公告)号：US20060179369A1

    公开(公告)日：2006-08-10

    申请号：US11055195

    申请日：2005-02-10

    申请人： Elianne Bravo ,  Kenneth Chan ,  Kevin Gower ,  Dustin VanStee

    发明人： Elianne Bravo ,  Kenneth Chan ,  Kevin Gower ,  Dustin VanStee

    IPC分类号： G11C29/00

    CPC分类号： G11C29/16 ,  G11C11/401

    摘要： A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

    摘要翻译： 用于测试动态随机存取存储器（DRAM）阵列的存储器内置自检（MBIST）装置和方法，所述DRAM阵列与包括接口逻辑和主线芯片逻辑的存储器接口装置通信。 MBIST装置包括有限状态机，其包括用于递增待测数据和地址的命令发生器和逻辑，以及与有限状态机通信的命令调度器。 命令调度器包括用于动态地利用DRAM时序参数将命令间隔到存储器的资源分配逻辑。 MBIST设备还包括存储MBIST测试的分测验的测试存储器。 每个分测验提供完整的配置地址范围。 MBIST装置还包括与测试存储器和有限状态机通信的子测试指针。 有限状态机通过子测验指针实现每个子测验的子测序。

    Delayed signal generation circuits and methods
    32.
    发明申请
    Delayed signal generation circuits and methods 失效
    延迟信号发生电路和方法

    公开(公告)号：US20060176090A1

    公开(公告)日：2006-08-10

    申请号：US11053695

    申请日：2005-02-08

    申请人： Kevin Gower ,  Swati Sathaye

    发明人： Kevin Gower ,  Swati Sathaye

    IPC分类号： H03L7/06

    CPC分类号： G06F1/04 ,  H03L7/06

    摘要： Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked loop output signals and outputs one or more buffered output signals. A multiplexing element receives the buffered output signals and a control signal and generates an operative buffered output signal in response to the control signal. A delay line receives a delay control input signal and the operative buffered output signal from the multiplexing element. The delay line outputs a delayed output signal in response to the delay control input signal.

    摘要翻译： 用于延迟信号的电路包括锁相环，其包括用于响应于参考信号输出一个或多个输出信号的一个或多个输出节点。 缓冲器耦合到锁相环的输出节点，用于接收锁相环输出信号并输出​​一个或多个缓冲输出信号。 多路复用元件接收缓冲的输出信号和控制信号，并响应于控制信号产生操作缓冲的输出信号。 延迟线从复用元件接收延迟控制输入信号和操作缓冲输出信号。 延迟线响应于延迟控制输入信号输出延迟的输出信号。

    System, method and storage medium for deriving clocks in a memory system
    34.
    发明申请
    System, method and storage medium for deriving clocks in a memory system 失效
    用于在存储器系统中导出时钟的系统，方法和存储介质

    公开(公告)号：US20070101086A1

    公开(公告)日：2007-05-03

    申请号：US11263344

    申请日：2005-10-31

    申请人： Frank Ferraiolo ,  Kevin Gower ,  Martin Schmatz

    发明人： Frank Ferraiolo ,  Kevin Gower ,  Martin Schmatz

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4234 ,  G06F13/1689

    摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.

    摘要翻译： 一种用于在存储器系统中导出时钟的系统，方法和存储介质。 该方法包括在集线器装置处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

    System, Method and storage medium for testing a memory module
    36.
    发明申请
    System, Method and storage medium for testing a memory module 失效
    用于测试内存模块的系统，方法和存储介质

    公开(公告)号：US20060117233A1

    公开(公告)日：2006-06-01

    申请号：US10977922

    申请日：2004-10-29

    申请人： Thomas Cowell ,  Frank Ferriaolo ,  Kevin Gower ,  Frank LaPietra

    发明人： Thomas Cowell ,  Frank Ferriaolo ,  Kevin Gower ,  Frank LaPietra

    IPC分类号： G01R31/28

    CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/022 ,  G11C2029/4002

    摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.

    摘要翻译： 包括下游缓冲器，下游接收器，上游驱动器，上游接收器的缓冲存储器模块。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。

    Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies
    39.
    发明申请
    Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies 失效
    固定延迟数据计算和芯片交叉电路和方法，用于支持多个参考振荡器频率的输出协议转换器的同步输入

    公开(公告)号：US20050268135A1

    公开(公告)日：2005-12-01

    申请号：US10853423

    申请日：2004-05-25

    申请人： Kirk Lamb ,  Kevin Gower ,  Thomas Griffin ,  Steven Hnatko ,  Dustin VanStee

    发明人： Kirk Lamb ,  Kevin Gower ,  Thomas Griffin ,  Steven Hnatko ,  Dustin VanStee

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12

    摘要： A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.

    摘要翻译： 支持多个参考振荡器频率和固定等待时间数据计算和芯片交叉电路的输出协议转换器的同步输入使得能够实现一种用于将相对于振荡器1的振荡器2延迟的方法 可配置的方式来在用于传送数据的电路之间的反射率范围内提供恒定的最小Ttcc。 它要求从寄存器R＆lt; 1＆gt; 1传送的数据通过多个导线通过用于osc 2 2的可配置延迟电路发送，在R 2的输入处的捕获电路 / SUB>，以及将同步信号从非延迟时钟域传送到延迟的时钟域的电路。 相对于osc <1> ，osc <2> 是延迟的同步时钟。

    SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING A HIGH SPEED TEST INTERFACE TO A MEMORY SUBSYSTEM
    40.
    发明申请
    SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING A HIGH SPEED TEST INTERFACE TO A MEMORY SUBSYSTEM 有权
    用于向存储器子系统提供高速测试界面的系统，方法和存储介质

    公开(公告)号：US20080104290A1

    公开(公告)日：2008-05-01

    申请号：US11971578

    申请日：2008-01-09

    申请人： Thomas Cowell ,  Kevin Gower ,  Frank LaPietra

    发明人： Thomas Cowell ,  Kevin Gower ,  Frank LaPietra

    IPC分类号： G06F13/12

    CPC分类号： G11C29/48 ,  G11C5/00 ,  G11C5/04 ,  G11C29/1201

    摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

    摘要翻译： 用于测试存储器子系统的缓冲设备。 缓冲装置包括适于连接到低速总线的并行总线端口和适于连接到高速总线的串行总线端口。 高速总线以比慢速总线更快的速度运行。 缓冲装置还包括总线转换器，其具有用于将经由串行总线端口接收的串行分组化输入数据转换为并行总线输出数据的标准操作模式，以经由并行总线端口输出。 缓冲装置还包括用于将经由并行总线端口接收的并行总线输入数据转换为串行分组化输出数据以供经由串行总线端口输出的备用操作模式。 串行打包输入数据在串行打包输出数据的功能和时序上是一致的。