公开(公告)号：US20050268135A1

公开(公告)日：2005-12-01

申请号：US10853423

申请日：2004-05-25

申请人： Kirk Lamb ,  Kevin Gower ,  Thomas Griffin ,  Steven Hnatko ,  Dustin VanStee

发明人： Kirk Lamb ,  Kevin Gower ,  Thomas Griffin ,  Steven Hnatko ,  Dustin VanStee

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.

摘要翻译： 支持多个参考振荡器频率和固定等待时间数据计算和芯片交叉电路的输出协议转换器的同步输入使得能够实现一种用于将相对于振荡器1的振荡器2延迟的方法 可配置的方式来在用于传送数据的电路之间的反射率范围内提供恒定的最小Ttcc。 它要求从寄存器R＆lt; 1＆gt; 1传送的数据通过多个导线通过用于osc 2 2的可配置延迟电路发送，在R 2的输入处的捕获电路 / SUB>，以及将同步信号从非延迟时钟域传送到延迟的时钟域的电路。 相对于osc <1> ，osc <2> 是延迟的同步时钟。

公开(公告)号：US20060164909A1

公开(公告)日：2006-07-27

申请号：US11041335

申请日：2005-01-24

申请人： Kevin Gower ,  Kirk Lamb ,  Dustin VanStee

发明人： Kevin Gower ,  Kirk Lamb ,  Dustin VanStee

IPC分类号： G11C8/00

CPC分类号： G11C7/1048 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： A memory system including a plurality of delay lines and a processor in communication with the delay lines. The delay lines are in communication with a bus attached to a memory device. The bus includes a plurality of wires and each of the delay lines corresponds to on of the plurality of wires. The processor receives a plurality of data bits and a data strobe via the wires on the bus. Each of the data bits includes data eye. The process also automatically calibrates the target data eye of each of the data bits and corresponds to the target data eye. In addition, the processor centers the data strobe over the target data eye.

摘要翻译： 一种包括多个延迟线的存储系统和与延迟线通信的处理器。 延迟线与连接到存储器件的总线通信。 总线包括多条导线，并且每条延迟线对应于多根线上的导线。 处理器经由总线上的电线接收多个数据位和数据选通。 每个数据位都包括数据眼。 该过程还自动校准每个数据位的目标数据眼，并对应于目标数据眼。 此外，处理器将数据选通中心对准目标数据眼睛。

公开(公告)号：US20060179369A1

公开(公告)日：2006-08-10

申请号：US11055195

申请日：2005-02-10

申请人： Elianne Bravo ,  Kenneth Chan ,  Kevin Gower ,  Dustin VanStee

发明人： Elianne Bravo ,  Kenneth Chan ,  Kevin Gower ,  Dustin VanStee

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C11/401

摘要： A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

摘要翻译： 用于测试动态随机存取存储器（DRAM）阵列的存储器内置自检（MBIST）装置和方法，所述DRAM阵列与包括接口逻辑和主线芯片逻辑的存储器接口装置通信。 MBIST装置包括有限状态机，其包括用于递增待测数据和地址的命令发生器和逻辑，以及与有限状态机通信的命令调度器。 命令调度器包括用于动态地利用DRAM时序参数将命令间隔到存储器的资源分配逻辑。 MBIST设备还包括存储MBIST测试的分测验的测试存储器。 每个分测验提供完整的配置地址范围。 MBIST装置还包括与测试存储器和有限状态机通信的子测试指针。 有限状态机通过子测验指针实现每个子测验的子测序。

公开(公告)号：US20070300018A1

公开(公告)日：2007-12-27

申请号：US11426616

申请日：2006-06-27

申请人： John Campbell ,  Kevin Gower

发明人： John Campbell ,  Kevin Gower

IPC分类号： G06F12/00

CPC分类号： G06F13/1673

摘要： A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.

摘要翻译： 一种存储器系统，包括具有第一端口和第二端口的缓冲器装置的第一存储器子系统，经由第二端口耦合到缓冲器装置的一个或多个存储器件，以及用于耦合到存储器的第一二合一链路 控制器，用于提供缓冲设备和存储器控制器之间的通信。 第一个二对一连接耦合到缓冲设备的第一个端口。 第一存储器子系统被配置为经由缓冲器设备在一个或多个存储器件的至少一个存储器件和存储器控制器之间传送数据。 第一个二对一连接包括多达两个连接到单个链路的收发器，至多两个收发器中的至少一个由两个或更多个用于发送信号的发射机中的任一个组成，或两个或更多个用于接收信号的接收机。

公开(公告)号：US20070286199A1

公开(公告)日：2007-12-13

申请号：US11843271

申请日：2007-08-22

申请人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

发明人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

IPC分类号： H04L12/56

CPC分类号： G06F13/1657 ,  G06F13/1673

摘要： A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags. The memory controller also includes a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller. Input to the determining includes an upstream identification tag included in the received data packet. If the received data packet is determined to be in response to a request from the memory controller, then the received data packet is matched to the request, thereby allowing the memory controller to operate with indeterminate data response times.

摘要翻译： 一种用于在具有不确定的数据响应时间的存储器系统中提供识别标签的方法和系统。 示例性实施例包括存储器系统中的存储器控​​制器。 存储器控制器包括用于经由上游信道接收数据分组的机制，所述数据分组包括上行识别标签。 存储器控制器还包括具有用于有助于确定接收的数据分组是否响应于来自存储器控制器的请求的指令的机制。 确定的输入包括包含在接收的数据分组中的上游标识标签。 如果接收到的数据分组被确定为响应于来自存储器控制器的请求，则接收的数据分组与该请求匹配，从而允许存储器控制器以不确定的数据响应时间进行操作。

公开(公告)号：US20070160053A1

公开(公告)日：2007-07-12

申请号：US11289193

申请日：2005-11-28

申请人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

发明人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

IPC分类号： H04L12/56 ,  H04L12/54

CPC分类号： G06F13/1657 ,  G06F13/1673

摘要： A method and system for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.

摘要翻译： 一种用于在存储器系统中提供不确定的读取数据等待时间的方法和系统。 该方法包括确定是否已经接收到本地数据分组。 如果接收到本地数据分组，则本地数据分组被存储到缓冲设备中。 该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上行驱动器空闲。 如果缓冲区包含数据包，并且上游驱动程序处于空闲状态，则将数据包传送到上游驱动程序。 该方法还包括确定是否已经接收到上游数据分组。 上行数据包是帧格式，包括帧开始指示符和存储器控制器在将上行数据包与其对应的读取指令相关联时使用的识别标签。 如果已经接收到上游数据分组，并且上游驱动程序不空闲，则上游数据分组被存储到缓冲设备中。 如果已经接收到上游数据分组，并且缓冲设备不包含数据分组，并且上游驱动器空闲，则将上游数据分组发送到上游驱动程序。 如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

公开(公告)号：US20060190780A1

公开(公告)日：2006-08-24

申请号：US11406717

申请日：2006-04-20

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

IPC分类号： G11C29/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

公开(公告)号：US20060176090A1

公开(公告)日：2006-08-10

申请号：US11053695

申请日：2005-02-08

申请人： Kevin Gower ,  Swati Sathaye

发明人： Kevin Gower ,  Swati Sathaye

IPC分类号： H03L7/06

CPC分类号： G06F1/04 ,  H03L7/06

摘要： Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked loop output signals and outputs one or more buffered output signals. A multiplexing element receives the buffered output signals and a control signal and generates an operative buffered output signal in response to the control signal. A delay line receives a delay control input signal and the operative buffered output signal from the multiplexing element. The delay line outputs a delayed output signal in response to the delay control input signal.

摘要翻译： 用于延迟信号的电路包括锁相环，其包括用于响应于参考信号输出一个或多个输出信号的一个或多个输出节点。 缓冲器耦合到锁相环的输出节点，用于接收锁相环输出信号并输出​​一个或多个缓冲输出信号。 多路复用元件接收缓冲的输出信号和控制信号，并响应于控制信号产生操作缓冲的输出信号。 延迟线从复用元件接收延迟控制输入信号和操作缓冲输出信号。 延迟线响应于延迟控制输入信号输出延迟的输出信号。

公开(公告)号：US20060036826A1

公开(公告)日：2006-02-16

申请号：US10903182

申请日：2004-07-30

申请人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1684

摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

摘要翻译： 用于提供总线速度倍增器的存储器子系统。 存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。 存储器子系统还包括存储器控制器和一个或多个存储器总线。 存储器总线的操作是内存模块数据速率的四倍。 存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。

公开(公告)号：US20080046796A1

公开(公告)日：2008-02-21

申请号：US11851527

申请日：2007-09-07

申请人： Timothy Dell ,  Kevin Gower ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Warren Maule

IPC分类号： H03M13/00

CPC分类号： G11C5/04

摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。