公开(公告)号：US20220102289A1

公开(公告)日：2022-03-31

申请号：US17405265

申请日：2021-08-18

Applicant: Tokyo Electron Limited

Inventor： Hojin Kim ,  Stephen Mancini ,  Soo Doo Chae

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/311 ,  H01L21/762

Abstract: This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.

公开(公告)号：US11243465B2

公开(公告)日：2022-02-08

申请号：US16221030

申请日：2018-12-14

Applicant: Tokyo Electron Limited

Inventor： Wanjae Park ,  Lior Huli ,  Soo Doo Chae

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  G03F7/075 ,  G03F7/09 ,  G03F7/11 ,  G03F7/16

Abstract: Embodiments of methods for patterning using enhancement of surface adhesion are presented. In an embodiment, a method for patterning using enhancement of surface adhesion may include providing an input substrate with an anti-reflective coating layer and an underlying layer. Such a method may also include performing a surface adhesion modification process on the substrate, the surface adhesion modification process utilizing a plasma treatment configured to increase an adhesion property of an anti-reflective coating layer without affecting downstream processes. In an embodiment, the method may also include performing a photoresist coating process, a mask exposure process, and a developing process to generate a target patterned structure in a photoresist layer on the substrate. In such embodiments, the method may include controlling operating parameters of the surface adhesion modification process to achieve target profiles of the patterned structure and substrate throughput objectives.

公开(公告)号：US20210265369A1

公开(公告)日：2021-08-26

申请号：US16800344

申请日：2020-02-25

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Sang Cheol Han ,  Youngwoo Park

IPC: H01L27/11524 ,  H01L27/11582

Abstract: Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.

公开(公告)号：US10217670B2

公开(公告)日：2019-02-26

申请号：US15697249

申请日：2017-09-06

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Satoru Nakamura ,  Soo Doo Chae ,  Akiteru Ko ,  Kaoru Maekawa ,  Gerrit J. Leusink

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

公开(公告)号：US20180068899A1

公开(公告)日：2018-03-08

申请号：US15697249

申请日：2017-09-06

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Satoru Nakamura ,  Soo Doo Chae ,  Akiteru Ko ,  Kaoru Maekawa ,  Gerrit J. Leusink

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.