公开(公告)号：US20080253192A1

公开(公告)日：2008-10-16

申请号：US12118330

申请日：2008-05-09

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C29/76 ,  G11C16/0483 ,  G11C29/82

摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence.

摘要翻译： 半导体集成电路装置包括具有多个块的存储单元阵列，存储单元，块替换信息寄存器组和坏块标志寄存器组。 存储单元包括可以注册块替换信息的块替换信息登记区域和可以注册坏块信息的坏块信息登记区域。 根据在引导顺序期间从存储单元读出的块替换信息来设置块替换信息寄存器组，并且根据读取的块替换信息和坏块信息两者来设置坏块标志寄存器组 在引导顺序期间从存储单元出来。

公开(公告)号：US07388782B2

公开(公告)日：2008-06-17

申请号：US11616112

申请日：2006-12-26

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C29/76 ,  G11C16/0483 ,  G11C29/82

摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence.

摘要翻译： 半导体集成电路装置包括具有多个块的存储单元阵列，存储单元，块替换信息寄存器组和坏块标志寄存器组。 存储单元包括可以注册块替换信息的块替换信息登记区域和可以注册坏块信息的坏块信息登记区域。 根据在引导顺序期间从存储单元读出的块替换信息来设置块替换信息寄存器组，并且根据读取的块替换信息和坏块信息两者来设置坏块标志寄存器组 在引导顺序期间从存储单元出来。

公开(公告)号：US07236424B2

公开(公告)日：2007-06-26

申请号：US11086444

申请日：2005-03-23

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C8/00 ,  G11C8/18

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元; 被配置为耦合到所述存储单元阵列的读出放大器电路; 设置在读出放大器电路和数据输入/输出端口之间的数据传输电路; 控制信号生成电路，被配置为基于外部提供的参考时钟信号生成多个控制信号，所述控制信号用于控制读出放大器电路的数据输入和输出以及数据传送电路中的数据传送定时; 以及内部时钟信号生成电路，被配置为基于用于作为控制信号的基础的参考时钟信号产生内部时钟信号，内部时钟信号具有与参考时钟信号相同的时钟周期和不具有恒定占空比的内部时钟信号 关于参考时钟信号的占空比。

公开(公告)号：US20060044874A1

公开(公告)日：2006-03-02

申请号：US11086444

申请日：2005-03-23

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元; 被配置为耦合到所述存储单元阵列的读出放大器电路; 设置在读出放大器电路和数据输入/输出端口之间的数据传输电路; 控制信号生成电路，被配置为基于外部提供的参考时钟信号生成多个控制信号，所述控制信号用于控制读出放大器电路的数据输入和输出以及数据传送电路中的数据传送定时; 以及内部时钟信号生成电路，被配置为基于用于作为控制信号的基础的参考时钟信号产生内部时钟信号，内部时钟信号具有与参考时钟信号相同的时钟周期和不具有恒定占空比的内部时钟信号 关于参考时钟信号的占空比。

公开(公告)号：US08477542B2

公开(公告)日：2013-07-02

申请号：US13271645

申请日：2011-10-12

申请人： Hiroyuki Nagashima ,  Naoya Tokiwa

发明人： Hiroyuki Nagashima ,  Naoya Tokiwa

IPC分类号： G11C8/08

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C5/04 ,  G11C8/04 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

摘要翻译： 半导体存储器件包括多层布置的多个存储层，每个存储层包括一个单元阵列，该单元阵列包含多条第一平行线，多条第二平行线与第一条线交叉，以及多个存储器 在第一线和第二线的交叉处连接的细胞; 脉冲发生器，用于产生数据访问存储单元所需的脉冲; 以及控制装置，用于控制脉冲发生器，使得从脉冲发生器输出的脉冲具有与存取目标存储单元所属的存储层相对应的能量。

公开(公告)号：US08446782B2

公开(公告)日：2013-05-21

申请号：US13271645

申请日：2011-10-12

申请人： Hiroyuki Nagashima ,  Naoya Tokiwa

发明人： Hiroyuki Nagashima ,  Naoya Tokiwa

IPC分类号： G11C8/08

摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

公开(公告)号：US08400814B2

公开(公告)日：2013-03-19

申请号：US12769991

申请日：2010-04-29

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C7/1042 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2211/5623 ,  G11C2211/5643 ,  G11C2213/71

摘要： A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other.

摘要翻译： 一种半导体存储器件包括由至少第一部分和第二部分构成的存储单元阵列，每个存储单元包括多个存储单元，每个存储器单元具有存储电可重写电阻值作为数据的可变电阻器，以及控制电路 第一操作包括用于擦除，写入和读取第一部分中的数据的操作中的一个操作，以及包括在第二部分中擦除，写入和读取数据的操作中的一个操作的第二操作，执行第一操作和第二操作 在时间上彼此重叠。

公开(公告)号：US08339853B2

公开(公告)日：2012-12-25

申请号：US13353047

申请日：2012-01-18

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.

公开(公告)号：US08339833B2

公开(公告)日：2012-12-25

申请号：US12708822

申请日：2010-02-19

申请人： Naoya Tokiwa ,  Hiroshi Maejima

发明人： Naoya Tokiwa ,  Hiroshi Maejima

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor storage device includes a memory core that includes plural banks, the bank including plural memory cells and a data write circuit that supplies a bias voltage to the memory cell, the memory core being logically divided into plural pages, the page including a predetermined number of memory cells belonging to a predetermined number of banks; and a control circuit that controls the data write circuit to perform page write in each write unit including a predetermined number of memory cells, pieces of data being written in the page in the page write, the control circuit performing the page write by repeating a step including a program operation and a verify operation, the control circuit performing the program operation and the verify operation in a next step or later only to the write unit in which the data write is not completed in the verify operation.

摘要翻译： 一种非易失性半导体存储装置，包括具有多个存储体的存储器芯，所述存储体包括多个存储单元，以及向所述存储单元提供偏置电压的数据写入电路，所述存储器核被逻辑地分割成多个页，所述页包括预定的 属于预定数量的存储体的存储单元的数量; 以及控制电路，其控制所述数据写入电路，在包括预定数量的存储器单元的每个写入单元中执行页写入，所述多个数据被写入所述页写入中，所述控制电路通过重复步骤 包括程序操作和验证操作，所述控制电路在下一步骤或稍后执行程序操作和验证操作仅在验证操作中仅写入数据写入的写入单元。

公开(公告)号：US07952958B2

公开(公告)日：2011-05-31

申请号：US12507366

申请日：2009-07-22

申请人： Kosuke Yanagidaira ,  Toshihiro Suzuki ,  Naoya Tokiwa

发明人： Kosuke Yanagidaira ,  Toshihiro Suzuki ,  Naoya Tokiwa

IPC分类号： G11C8/00

CPC分类号： G11C16/349

摘要： There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile memory comprises a status output section configured to output status information indicating a status of read operation, write operation or erase operation in the non-volatile memory cell. The controller comprises a control signal generating section configured to output a control signal for a certain operation in the non-volatile memory, and a control signal switching section configured to instruct the control signal generating section to switch the control signal based on the status information.

摘要翻译： 提供了一种其中布置有电可重写非易失性存储单元的非易失性存储器。 控制器控制非易失性存储器的操作。 非易失性存储器包括状态输出部分，被配置为在非易失性存储器单元中输出指示读取操作，写入操作或擦除操作的状态的状态信息。 所述控制器包括：控制信号生成部，被配置为输出用于所述非易失性存储器中的某个操作的控制信号;以及控制信号切换部，被配置为指示所述控制信号生成部基于所述状态信息来切换所述控制信号。