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    Semiconductor memory and a method of manufacturing the same
    32.
    发明授权
    Semiconductor memory and a method of manufacturing the same 失效
    半导体存储器及其制造方法

    公开(公告)号：US5892256A

    公开(公告)日：1999-04-06

    申请号：US804747

    申请日：1997-02-21

    申请人： Takeshi Matsushita ,  Muneharu Shimanoe ,  Hiroshi Sato ,  Akira Nieda

    发明人： Takeshi Matsushita ,  Muneharu Shimanoe ,  Hiroshi Sato ,  Akira Nieda

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/1082 ,  H01L27/10832

    摘要： A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.

    摘要翻译： 一种具有由MIS晶体管和电容器组成的存储单元的半导体存储器及其制造方法。 半导体存储器包括半导体衬底，形成在半导体衬底上的绝缘层和形成在绝缘层的表面上的半导体区域。 半导体存储器的特征在于，MIS晶体管分别形成在半导体区域的表面上并且通过绝缘层彼此分离并且与半导体衬底分离，并且电容器分别形成在相应的MIS晶体管 。 将MIS晶体管彼此分开并从半导体衬底分离的绝缘层减少了存储单元之间的电流泄漏，并降低了在MIS晶体管和半导体衬底侧形成的位线之间的电容。 半导体存储器的制造方法包括：在由绝缘层形成的凹部中形成半导体区域时研磨晶片的表面的研磨工艺。 研磨过程使用碱性液体作为研磨液，并使用配有硬研磨垫的研磨盘，通过研磨完成与绝缘层表面齐平的半导体区域的表面。

    Semiconductor memory cell having information storage transistor and switching transistor
    34.
    发明授权
    Semiconductor memory cell having information storage transistor and switching transistor 失效

    公开(公告)号：US5578852A

    公开(公告)日：1996-11-26

    申请号：US541127

    申请日：1995-10-11

    申请人： Yutaka Hayashi ,  Takeshi Matsushita

    发明人： Yutaka Hayashi ,  Takeshi Matsushita

    IPC分类号： G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L31/0392

    CPC分类号： H01L27/108 ,  G11C11/404

    摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

    Semiconductor memory cell having information storage transistor and switching transistor
    35.
    发明授权
    Semiconductor memory cell having information storage transistor and switching transistor 失效
    具有信息存储晶体管和开关晶体管的半导体存储单元

    公开(公告)号：US5576571A

    公开(公告)日：1996-11-19

    申请号：US541173

    申请日：1995-10-11

    申请人： Yutaka Hayashi ,  Takeshi Matsushita

    发明人： Yutaka Hayashi ,  Takeshi Matsushita

    IPC分类号： G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L27/108 ,  G11C11/404

    摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.1, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

    摘要翻译： 提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许 短通道设计，并且可以减小单元格区域。 半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L1，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和 第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L2连接到固定 电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

    Semiconductor memory cell
    36.
    发明授权
    Semiconductor memory cell 失效
    半导体存储单元

    公开(公告)号：US5506436A

    公开(公告)日：1996-04-09

    申请号：US420068

    申请日：1995-04-11

    申请人： Yutaka Hayashi ,  Takeshi Matsushita

    发明人： Yutaka Hayashi ,  Takeshi Matsushita

    IPC分类号： G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

    CPC分类号： H01L27/108 ,  G11C11/404

    摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub. 2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

    摘要翻译： 提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许 短通道设计，并且可以减小单元格区域。 半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L3，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和 第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L 2连接到 固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

    Method for production of SOI transistor device having a storage cell
    38.
    发明授权
    Method for production of SOI transistor device having a storage cell 失效
    具有存储单元的SOI晶体管器件的制造方法

    公开(公告)号：US5427973A

    公开(公告)日：1995-06-27

    申请号：US230713

    申请日：1994-04-21

    申请人： Hiroshi Satoh ,  Yasunori Ohokubo ,  Takeshi Matsushita ,  Toshiyuki Nishihara ,  Makoto Hashimoto

    发明人： Hiroshi Satoh ,  Yasunori Ohokubo ,  Takeshi Matsushita ,  Toshiyuki Nishihara ,  Makoto Hashimoto

    IPC分类号： H01L29/772 ,  H01L21/762 ,  H01L23/544 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L23/544 ,  H01L21/76251 ,  H01L27/1082 ,  H01L27/10832 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S438/975 ,  Y10S438/977

    摘要： A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique storage node having a conductive side wall.

    摘要翻译： 一种用于形成SOI结构的晶片接合方法，包括以下步骤：使晶片在与一个晶片的状态相接近的状态下与另一个晶片略微，基本上均匀的间隙，并将两个晶片的至少一个晶片的一个点压在另一个晶片上 晶圆。 在本发明的另一方面，提供了一种使用在SOI衬底上形成的对准标记部分和/或游标部分进行光刻定位的方法，其包括以下步骤：去除对准标记部分对应的半导体层部分和/ 或游标部分。 在本发明的另一方面，提供了一种通过使用SOI结构形成的新的DRAM半导体器件，其包括沿字线纵向形成的栅格节点的新图案。 此外，提供了通过使用SOI结构形成的新的DRAM半导体器件，其包括具有导电侧壁的唯一存储节点。

    Method of making a DRAM cell
    39.
    发明授权
    Method of making a DRAM cell 失效
    制造DRAM单元的方法

    公开(公告)号：US5102819A

    公开(公告)日：1992-04-07

    申请号：US644448

    申请日：1991-01-23

    申请人： Takeshi Matsushita ,  Muneharu Shimanoe ,  Hiroshi Sato ,  Akira Nieda

    发明人： Takeshi Matsushita ,  Muneharu Shimanoe ,  Hiroshi Sato ,  Akira Nieda

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/1082 ,  H01L27/10832

    摘要： A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.