公开(公告)号：US07821824B2

公开(公告)日：2010-10-26

申请号：US12258964

申请日：2008-10-27

申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

公开(公告)号：US20070247918A1

公开(公告)日：2007-10-25

申请号：US11573004

申请日：2004-08-30

申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC分类号： G11C11/34

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储区域以加快存储器信息的读取速度，并且可以优先考虑第二非易失性存储器区域以保证存储器信息的重写操作的次数更多。

公开(公告)号：US06459619B1

公开(公告)日：2002-10-01

申请号：US09986081

申请日：2001-11-07

申请人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for-each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

摘要翻译： 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且每个存储器单元的阈值电压被管理在所选存储器块中的每个字线。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US06711061B2

公开(公告)日：2004-03-23

申请号：US10223488

申请日：2002-08-20

申请人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

摘要翻译： 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US06842376B2

公开(公告)日：2005-01-11

申请号：US10638491

申请日：2003-08-12

申请人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/02 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

摘要翻译： 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US07110295B2

公开(公告)日：2006-09-19

申请号：US11002802

申请日：2004-12-03

申请人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

发明人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/30

摘要： An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

摘要翻译： 分配擦除电流以减少内部电源电路的负载并减少用于擦除的驱动器的数量。 一种半导体数据处理装置具有：存储阵列，其具有排列成矩阵状的非易失性存储单元，分为多个擦除块，分别被指示一起擦除; 以及控制电路，其中控制电路控制施加到擦除块中的非易失性存储单元的两种擦除电压，这些擦除块被一起擦除，以从擦除块中选择擦除扇区，以便为每个擦除扇区执行擦除，从而 按时间划分每个擦除扇区的擦除。 时分擦除可以分配擦除电流。 使用两种擦除电压来选择擦除扇区。 没有为每个擦除扇区提供特定的驱动程序。

公开(公告)号：US20050128815A1

公开(公告)日：2005-06-16

申请号：US11002802

申请日：2004-12-03

申请人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

发明人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C16/06 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/16 ,  G11C16/30

摘要： An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

摘要翻译： 分配擦除电流以减少内部电源电路的负载并减少用于擦除的驱动器的数量。 一种半导体数据处理装置具有：存储阵列，其具有排列成矩阵状的非易失性存储单元，分为多个擦除块，分别被指示一起擦除; 以及控制电路，其中控制电路控制施加到擦除块中的非易失性存储单元的两种擦除电压，这些擦除块被一起擦除，以从擦除块中选择擦除扇区，以便为每个擦除扇区执行擦除，从而 按时间划分每个擦除扇区的擦除。 时分擦除可以分配擦除电流。 使用两种擦除电压来选择擦除扇区。 没有为每个擦除扇区提供特定的驱动程序。

公开(公告)号：US08050085B2

公开(公告)日：2011-11-01

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C7/10 ,  G11C11/40

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US20090213649A1

公开(公告)日：2009-08-27

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/14 ,  G06F12/14

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US06519184B2

公开(公告)日：2003-02-11

申请号：US10082335

申请日：2002-02-26

申请人： Toshihiro Tanaka ,  Hiroyuki Tanikawa ,  Masayoshi Nakano ,  Norio Oza ,  Koki Watanabe ,  Yutaka Shinagawa

发明人： Toshihiro Tanaka ,  Hiroyuki Tanikawa ,  Masayoshi Nakano ,  Norio Oza ,  Koki Watanabe ,  Yutaka Shinagawa

IPC分类号： G11C1606

CPC分类号： G11C16/344 ,  G11C16/3468

摘要： In a verify operation after a write or erase to check whether a memory cell threshold voltage is contained in a predetermined threshold voltage distribution, verify voltage is changed in three stages or more in a direction to mitigate the decision condition. This prevents non-convergence of write and erase operation and can complete the write or erase in a short time.