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公开(公告)号：US06992929B2
公开(公告)日：2006-01-31
申请号：US10803183
申请日：2004-03-17
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译： 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。
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公开(公告)号：US20060017085A1
公开(公告)日：2006-01-26
申请号：US10900413
申请日：2004-07-26
申请人： Prateep Tuntasood , Der-Tsyr Fan , Chiou-Feng Chen
发明人： Prateep Tuntasood , Der-Tsyr Fan , Chiou-Feng Chen
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.
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33.发明申请公开(公告)号：US20050276106A1
公开(公告)日：2005-12-15
申请号：US10869475
申请日：2004-06-15
申请人： Chiou-Feng Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： G11C11/34 , G11C16/04 , H01L21/8246 , H01L27/105 , H01L27/115
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11519 , H01L27/11568
摘要： NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.
摘要翻译： NAND闪速存储单元阵列具有控制栅极和电荷存储门，它们成对地排列成位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的栅极彼此自对准，并且电荷存储栅极是氮化物或氮化物和氧化物的组合。 通过从硅衬底到电荷存储门的热电子注入来完成编程，以在电荷存储门中建立负电荷。 通过从电荷存储栅极到硅衬底的沟道隧穿或通过从硅衬底到电荷存储栅的热空穴注入来完成擦除。 该阵列被偏置，使得所有的存储单元可以同时被擦除，而编程是位可选择的。
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公开(公告)号：US20050146937A1
公开(公告)日：2005-07-07
申请号：US11059475
申请日：2005-02-16
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.
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公开(公告)号：US06894339B2
公开(公告)日：2005-05-17
申请号：US10336639
申请日：2003-01-02
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.
摘要翻译： 闪存和制造过程，其中在堆叠的，自对准的浮动和控制栅极之间的沟槽中用选择栅极形成存储器单元，其中由选择栅极选通的掩埋的源极和漏极区域。 擦除路径形成在浮动栅极和选择栅极的突出的圆形边缘之间，并且编程路径从选择栅极之间的中间沟道区域和通过栅极氧化物的浮动栅极延伸到浮动栅极的边缘。 根据阵列结构，可以在浮动和控制栅极的一侧或两侧设置倾斜的选择栅极，并且在蚀刻衬底和其它材料以形成沟槽时将堆叠的栅极和覆盖它们的电介质用作自对准掩模 。
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36.发明授权公开(公告)号：US06747310B2
公开(公告)日：2004-06-08
申请号：US10267014
申请日：2002-10-07
申请人： Der-Tsyr Fan , Chiou-Feng Chen , Prateep Tuntasood
发明人： Der-Tsyr Fan , Chiou-Feng Chen , Prateep Tuntasood
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L29/42328 , H01L29/7883
摘要： Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates. These memory cells are very small in size and provide substantially better programming and erase performance than memory cells of the prior art.
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37.发明授权Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide 失效多晶硅发射极和多晶硅栅极，其在薄栅极氧化物上使用相同的多晶硅蚀刻
公开(公告)号：US5124817A
公开(公告)日：1992-06-23
申请号：US694744
申请日：1991-05-02
IPC分类号： H01L21/28 , H01L21/311 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/28035 , H01L21/31116 , H01L21/8249 , H01L27/0623
摘要： Bipolar and MOS devices are made simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.
摘要翻译： 使用单个制造工艺同时制作双极和MOS器件。 在本发明的一个实施例中，硅衬底被分为双极和MOS区。 在硅衬底上热生长厚度在大约150埃至300埃范围内的薄层栅极氧化物。 厚度在大约500埃至1000埃范围内的多晶硅薄层沉积在栅极氧化物层上，以在随后的处理期间保护栅极氧化物层。 从形成发射极的双极区域去除薄多晶硅层和栅极氧化物层。 为了在蚀刻期间保持栅极氧化物层的完整性，在栅极氧化物蚀刻期间保留在多晶硅蚀刻期间使用的光致抗蚀剂掩模，并且在缓冲的氧化物溶液中蚀刻栅极氧化物。 然后将厚的多晶硅层沉积在硅衬底的双极和MOS区上，并且掩模和蚀刻衬底以形成双极和MOS器件的发射极和栅极。
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