公开(公告)号：US20110090617A1

公开(公告)日：2011-04-21

申请号：US12686399

申请日：2010-01-13

Applicant: Shin-Bin Huang ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Chung-Lin Huang

IPC: H01G4/005 ,  H01G4/00

CPC classification number: H01G4/33 ,  H01G4/005 ,  H01G4/228 ,  H01L23/50 ,  H01L27/10852 ,  H01L28/88 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a capacitor electrode. A stack structure is formed on a substrate, and the stack structure includes a first conductive layer, a first sacrificial layer, and a second sacrificial layer. The stack structure includes a first sidewall and a second sidewall facing the first sidewall. A conductive sidewall is formed on the first sidewall and the second sidewall to electrically connect the first conductive layer to the second conductive layer. Finally, the first and the second sacrificial layers are removed.

Abstract translation: 一种制造电容器电极的方法。 堆叠结构形成在衬底上，堆叠结构包括第一导电层，第一牺牲层和第二牺牲层。 堆叠结构包括第一侧壁和面向第一侧壁的第二侧壁。 导电侧壁形成在第一侧壁和第二侧壁上，以将第一导电层电连接到第二导电层。 最后，去除第一和第二牺牲层。

公开(公告)号：US20100279472A1

公开(公告)日：2010-11-04

申请号：US12838495

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/8239

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

Abstract translation: 在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。 包括存储单元列的第一存储器阵列形成在衬底上。 每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨过存储器单元延伸的控制栅极线 列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。 第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。 每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

公开(公告)号：US07713820B2

公开(公告)日：2010-05-11

申请号：US11945199

申请日：2007-11-26

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

Abstract translation: 提供一种用于制造非易失性存储器的方法。 在衬底中形成的沟槽中形成隔离结构。 去除隔离结构的一部分以形成凹部。 在基板上依次形成第一介电层和第一导电层。 在基板上形成棒状盖层。 未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层。 在第一栅极结构之间的衬底上形成第三电介质层。 在第三电介质层上形成第二导电层。 条形盖层和第一导电层的一部分被去除以形成第二栅极结构。 在每个第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20090032858A1

公开(公告)日：2009-02-05

申请号：US11927616

申请日：2007-10-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅极晶体管的选择栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US20070063260A1

公开(公告)日：2007-03-22

申请号：US11603771

申请日：2006-11-22

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US06900112B2

公开(公告)日：2005-05-31

申请号：US10426348

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A process for forming shallow trench isolation region with corner protection layer. A protection layer is formed within the opening that defines the isolation trench as part of the etching mask such that the etching rate of the protection layer is less than the mask layer and the pad insulating layer to the etchant used to remove the mask layer and pad insulating layer. The protection layer is partially removed and left adjacent to the shallow trench isolation region as a corner protection layer after removing the mask layer and pad insulating layer. Thus, the indentation next to the corner of the isolation region is avoided.

Abstract translation: 用于形成具有角保护层的浅沟槽隔离区的工艺。 在开口内形成保护层，其将隔离沟槽定义为蚀刻掩模的一部分，使得保护层的蚀刻速率小于用于去除掩模层和焊盘的掩模层和蚀刻剂的焊盘绝缘层 绝缘层。 在去除掩模层和焊盘绝缘层之后，保护层被部分地去除并且与作为转角保护层的浅沟槽隔离区相邻。 因此，避免了隔离区域的拐角附近的压痕。

公开(公告)号：US20050101090A1

公开(公告)日：2005-05-12

申请号：US11014483

申请日：2004-12-15

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L29/40114

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

Abstract translation: 具有多个尖端的浮动栅极及其制造方法。 提供半导体衬底，在其上形成图案化的硬掩模层，其中图案化的硬掩模层具有开口。 在开口的底部形成具有第一预定厚度的栅介质层和第一导电层。 间隔件形成在开口的侧壁上。 导电间隔件形成在间隔件的侧壁上。 第一导电层被蚀刻到第二预定厚度。 由第一导电层和导电间隔物提供多尖端浮栅。 在开口中形成保护层。 蚀刻图案化的硬掩模层，栅介质层，保护层的一部分和第一间隔物的一部分，以露出第一导电层的表面。

公开(公告)号：US06800526B2

公开(公告)日：2004-10-05

申请号：US10302865

申请日：2002-11-25

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

Abstract translation: 一种分离栅闪存单元的制造方法，包括以下步骤：在半导体衬底上形成有源区; 在半导体衬底上形成缓冲层; 在缓冲层上形成第一介电层; 去除所述第一电介质层的一部分; 定义一个开口 去除开口内的缓冲层; 形成栅绝缘层和浮栅; 在所述半导体衬底中形成源区; 在开口上沉积共形的第二介电层; 去除第一介电层和浮栅之外的缓冲层; 并形成氧化物层和控制栅极。

公开(公告)号：US06673676B2

公开(公告)日：2004-01-06

申请号：US10229529

申请日：2002-08-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

Abstract translation: 一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 在所述第一栅极绝缘层上形成第一导电层; 形成浮栅绝缘层; 通过将杂质离子注入衬底来形成源区; 形成第二绝缘层; 形成浮栅区域; 形成第三绝缘层; 在所述第三绝缘层上形成第二导电层; 在所述第二导电层上形成第四绝缘层; 形成浮栅区域; 在所述第三绝缘层上形成第二导电层; 形成第一侧壁间隔物; 形成控制栅极和隧道氧化物; 形成第二侧壁间隔物; 以及在所述衬底上形成漏区。

公开(公告)号：US06403483B1

公开(公告)日：2002-06-11

申请号：US09695144

申请日：2000-10-25

Applicant: Chung-Peng Hao ,  Chung-Lin Huang ,  Chung-Yuan Lee ,  Yih-Ren Shao ,  Pei-Ing Lee

Inventor： Chung-Peng Hao ,  Chung-Lin Huang ,  Chung-Yuan Lee ,  Yih-Ren Shao ,  Pei-Ing Lee

IPC: H01L21302

CPC classification number: H01L21/76897 ,  H01L21/76224

Abstract: A shallow trench isolation having an etching stop layer and its method of fabrication. The method utilizes a shield layer such as a silicon nitride layer to serve as an etching stop layer. The etching stop layer is formed in the top position of the shallow trench isolation.

Abstract translation: 具有蚀刻停止层的浅沟槽隔离及其制造方法。 该方法利用诸如氮化硅层的屏蔽层作为蚀刻停止层。 蚀刻停止层形成在浅沟槽隔离的顶部位置。