公开(公告)号：US11195831B2

公开(公告)日：2021-12-07

申请号：US16596764

申请日：2019-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L29/778 ,  H01L27/06 ,  H01L27/085 ,  H01L29/66

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US10991757B2

公开(公告)日：2021-04-27

申请号：US16430437

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

公开(公告)号：US20210082911A1

公开(公告)日：2021-03-18

申请号：US16596764

申请日：2019-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/66 ,  H01L27/085

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US20180151555A1

公开(公告)日：2018-05-31

申请号：US15365906

申请日：2016-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Chih-Kai Kang ,  Wen-Kai Lin ,  Shu-Hung Yu

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76897 ,  H01L23/5283 ,  H01L28/60 ,  H01L29/0649

Abstract: An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.

公开(公告)号：US20250089281A1

公开(公告)日：2025-03-13

申请号：US18487110

申请日：2023-10-15

Applicant: United Microelectronics Corp.

Inventor： Wen-Kai Lin ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/47 ,  H01L29/66

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate including a fin portion, first and second doped regions having a first conductive type, first and second contacts, and first and second metal silicide layers. The fin portion protrudes from a surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region. A doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.

公开(公告)号：US11895847B2

公开(公告)日：2024-02-06

申请号：US17987795

申请日：2022-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/10 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US20230317715A1

公开(公告)日：2023-10-05

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/94 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/7851 ,  H01L29/66181 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

公开(公告)号：US11631761B2

公开(公告)日：2023-04-18

申请号：US17676867

申请日：2022-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

公开(公告)号：US11296036B2

公开(公告)日：2022-04-05

申请号：US16986270

申请日：2020-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Kang ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Kuo-Yu Liao ,  Shu-Hung Yu ,  Hung-Hsu Lin ,  Hsiang-Hung Peng

IPC: H01L23/544 ,  H01L27/092 ,  H01L27/02 ,  G03F9/00 ,  H01L21/8238

Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

公开(公告)号：US20220059528A1

公开(公告)日：2022-02-24

申请号：US17516721

申请日：2021-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L27/06 ,  H01L27/085 ,  H01L29/66 ,  H01L29/778

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.