公开(公告)号：US11631679B2

公开(公告)日：2023-04-18

申请号：US17741431

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

公开(公告)号：US11502180B2

公开(公告)日：2022-11-15

申请号：US16792308

申请日：2020-02-17

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Wei Wu ,  Ting-Pang Chung ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/423 ,  H01L21/02 ,  H01L27/108 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L27/11568 ,  H01L27/11578

Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

公开(公告)号：US10608086B2

公开(公告)日：2020-03-31

申请号：US15854769

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L21/265 ,  H01L29/423 ,  H01L29/08 ,  H01L21/223 ,  H01L29/167 ,  H01L23/535

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.

公开(公告)号：US20190312036A1

公开(公告)日：2019-10-10

申请号：US16443880

申请日：2019-06-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tsuo-Wen Lu ,  Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

公开(公告)号：US20190181141A1

公开(公告)日：2019-06-13

申请号：US16175851

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench

公开(公告)号：US20190067293A1

公开(公告)日：2019-02-28

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US20190013204A1

公开(公告)日：2019-01-10

申请号：US15659653

申请日：2017-07-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tien-Chen Chan ,  Ger-Pin Lin ,  Tsuo-Wen Lu ,  Chin-Wei Wu ,  Yu-Chun Wang ,  Shu-Yen Chan

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/74 ,  H01L23/535 ,  H01L29/78

Abstract: A method of fabricating a buried word line includes forming a trench in a substrate. Next, a deposition process is performed to form a silicon layer on a sidewall and a bottom at the inner side of the trench. After the deposition process, a gate dielectric layer is formed in the trench. Finally, a conductive layer is formed to fill in the trench.

公开(公告)号：US20180212030A1

公开(公告)日：2018-07-26

申请号：US15873904

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Wei Wu ,  Ting-Pang Chung ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08

CPC classification number: H01L29/4236 ,  H01L21/02233 ,  H01L21/02244 ,  H01L21/02255 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/12 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/4908

Abstract: A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer.

公开(公告)号：US20180190661A1

公开(公告)日：2018-07-05

申请号：US15854816

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yung-Ming Wang ,  Li-Wei Liu ,  Shu-Yen Chan ,  Yukihiro Nagai ,  Tien-Chen Chan ,  Ger-Pin Lin

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/10876 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28211 ,  H01L21/2822 ,  H01L27/10823 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; performing an ion implantation process to implant ions into the substrate underneath the trench; performing an in-situ steam generation (ISSG) process to form a gate dielectric layer in the trench; forming a gate electrode on the gate dielectric layer; and forming a doped region in the substrate adjacent to two sides of the gate electrode.

公开(公告)号：US20170373191A1

公开(公告)日：2017-12-28

申请号：US15214429

申请日：2016-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Li-Wei Feng ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.