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公开(公告)号：US11380780B2
公开(公告)日：2022-07-05
申请号：US16992352
申请日：2020-08-13
发明人： Fujio Masuoka , Nozomu Harada , Yoshiaki Kikuchi
IPC分类号： H01L29/66 , H01L21/225 , H01L21/308 , H01L21/02 , H01L21/306 , H01L29/423 , H01L29/786
摘要： A SiO2 layer 5 is formed in the bottom portion of a Si pillar 3 and on an i-layer substrate 2. Subsequently, a gate HfO2 layer 11b is formed so as to surround the side surface of the Si pillar 3, and a gate TiN layer 12b is formed so as to surround the HfO2 layer 11b. Subsequently, P+ layers 18 and 32 containing an acceptor impurity at a high concentration and serving as a source and a drain are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar 3. Thus, an SGT is formed on the i-layer substrate 2.
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公开(公告)号：US10937902B2
公开(公告)日：2021-03-02
申请号：US15968991
申请日：2018-05-02
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/78 , H01L21/3105 , H01L21/3213 , H01L29/66 , H01L29/417 , H01L29/08 , H01L29/423
摘要： A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.
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公开(公告)号：US10923591B2
公开(公告)日：2021-02-16
申请号：US16587728
申请日：2019-09-30
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/78 , H01L21/768 , H01L29/66 , H01L21/027 , H01L21/3105 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/8234 , H01L23/528 , H01L27/088
摘要： A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.
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公开(公告)号：US10734391B2
公开(公告)日：2020-08-04
申请号：US16238816
申请日：2019-01-03
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L21/225 , H01L27/11 , H01L23/485 , H01L29/423 , H01L21/768 , H01L23/522 , H01L29/66 , H01L29/78 , H01L21/20 , H01L21/28 , H01L21/285 , H01L21/76 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L23/528 , H01L29/04 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/49 , H01L21/308 , H01L21/8238 , H01L29/16 , H01L29/51 , H01L21/311 , H01L23/532
摘要： A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.
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公开(公告)号：US10658371B2
公开(公告)日：2020-05-19
申请号：US16225146
申请日：2018-12-19
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L21/225 , H01L27/11 , H01L29/786 , H01L21/324 , H01L21/8238 , H01L23/522 , H01L23/528 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/66
摘要： A method for producing a pillar-shaped semiconductor device includes, forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate. A gate insulating layer and gate conductor layer are formed surrounding each of the pillars and impurity regions are formed in each pillar. The gate conductor layer is selectively processed to form gate conductors around the pillars and to interconnect the gate conductors.
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公开(公告)号：US10651189B2
公开(公告)日：2020-05-12
申请号：US16148099
申请日：2018-10-01
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L27/1157 , H01L29/792 , H01L27/11582 , H01L27/11565 , H01L21/28 , H01L27/11575 , H01L27/11573
摘要： A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.
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公开(公告)号：US10593682B2
公开(公告)日：2020-03-17
申请号：US16296564
申请日：2019-03-08
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L21/285 , H01L27/11 , H01L29/423 , H01L29/786 , H01L21/768 , H01L23/522 , H01L23/528 , H01L29/78 , H01L29/45 , H01L29/49
摘要： A method for producing a semiconductor memory device includes forming two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.
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公开(公告)号：US10483376B1
公开(公告)日：2019-11-19
申请号：US16520892
申请日：2019-07-24
发明人： Fujio Masuoka , Hiroki Nakamura , Nozomu Harada
IPC分类号： H01L29/66 , H01L29/78 , H01L21/3213 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8234 , H01L21/28 , H01L29/06
摘要： A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
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公开(公告)号：US10475922B2
公开(公告)日：2019-11-12
申请号：US15800913
申请日：2017-11-01
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/78 , H01L29/66 , H01L21/027 , H01L21/3105 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/8234 , H01L23/528 , H01L27/088 , H01L21/768
摘要： A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a first insulating film around the fin-shaped semiconductor layer. A first contact is on the fin-shaped semiconductor layer, where the first contact is metal contact. A first gate insulating film is around the first contact and a fourth contact on the first contact, and a second gate insulating film is around the fourth contact.
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公开(公告)号：US10453941B2
公开(公告)日：2019-10-22
申请号：US15849026
申请日：2017-12-20
发明人： Fujio Masuoka , Hiroki Nakamura , Nozomu Harada
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L21/3213 , H01L29/423 , H01L29/786 , H01L29/78 , H01L29/06
摘要： A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
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