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公开(公告)号：US10553715B2
公开(公告)日：2020-02-04
申请号：US15917168
申请日：2018-03-09
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L29/78 , H01L29/66 , H01L21/461 , H01L21/475 , H01L29/423 , H01L21/8238 , H01L29/786 , H01L29/417 , H01L29/10 , H01L29/775 , H01L29/06
摘要： An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.
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公开(公告)号：US10535756B2
公开(公告)日：2020-01-14
申请号：US16241332
申请日：2019-01-07
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/423 , H01L21/225 , H01L21/308 , H01L29/40
摘要： The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.
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公开(公告)号：US10340184B2
公开(公告)日：2019-07-02
申请号：US16230151
申请日：2018-12-21
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L27/115 , H01L21/768 , H01L29/78 , H01L29/66
摘要： A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.
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公开(公告)号：US10056471B2
公开(公告)日：2018-08-21
申请号：US15342237
申请日：2016-11-03
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/423 , H01L29/66 , H01L21/28 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L21/28114 , H01L29/42356 , H01L29/42364 , H01L29/42392 , H01L29/6653 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/7827 , H01L29/785 , H01L29/78618 , H01L29/78642 , H01L29/78654 , H01L29/78696 , H01L2029/7858
摘要： A semiconductor device includes a fin-shaped semiconductor layer and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal gate line is connected to a metal gate electrode and extends in a direction perpendicular to a direction that of the fin-shaped semiconductor layer. A width of a bottom of the pillar-shaped semiconductor layer in a direction parallel to a direction in which the metal gate line extends is equal to a width of a top of the fin-shaped semiconductor layer in the direction parallel to the direction of the metal gate line. A gate insulating film is in contact with an underside of the gate electrode and the gate line and separates the metal gate electrode and the metal gate line from the fin-shaped semiconductor layer and a first insulating film. An outer width of the metal gate electrode is equal to a width of the metal gate line.
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公开(公告)号：US10026739B2
公开(公告)日：2018-07-17
申请号：US15610882
申请日：2017-06-01
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L27/092 , H01L29/786 , H01L29/423 , H01L29/45 , H01L29/49 , H01L23/528
摘要： A semiconductor device includes a first pillar-shaped semiconductor layer in which a second first-conductivity-type semiconductor layer, a first body region, a third first-conductivity-type semiconductor layer, a fourth first-conductivity-type semiconductor layer, a second body region, a fifth first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a third body region, and a second second-conductivity-type semiconductor layer are formed from a substrate side in this order; first, second, and third gates formed around first, second, third gate insulating films formed around the first, second, and third body regions, respectively; a first output terminal connecting the fifth first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; a second pillar-shaped semiconductor layer, on the first output terminal, in which a third second-conductivity-type semiconductor layer, a fourth body region, and a fourth second-conductivity-type semiconductor layer are formed from the substrate side in this order; and a fourth gate insulating film formed around the fourth body region.
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公开(公告)号：US09991381B2
公开(公告)日：2018-06-05
申请号：US14797839
申请日：2015-07-13
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/76 , H01L29/78 , H01L21/3105 , H01L21/3213 , H01L29/66 , H01L29/417 , H01L29/08 , H01L29/423
CPC分类号： H01L29/7827 , H01L21/31051 , H01L21/31055 , H01L21/32133 , H01L29/0847 , H01L29/41741 , H01L29/42356 , H01L29/66545 , H01L29/66666
摘要： A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.
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公开(公告)号：US09954032B2
公开(公告)日：2018-04-24
申请号：US15643031
申请日：2017-07-06
发明人： Fujio Masuoka , Hiroki Nakamura
CPC分类号： H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/128 , H01L45/1286 , H01L45/144 , H01L45/1658 , H01L45/1675
摘要： A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.
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公开(公告)号：US09929341B2
公开(公告)日：2018-03-27
申请号：US15489108
申请日：2017-04-17
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L31/062 , H01L31/0392 , H01L21/00 , H01L21/8238 , H01L21/336 , H01L45/00 , H01L21/02 , C30B29/46 , C23C16/30 , H01L21/762
CPC分类号： H01L45/1233 , C23C16/305 , C30B29/46 , H01L21/02417 , H01L21/02568 , H01L21/76208 , H01L27/2454 , H01L29/66545 , H01L29/66666 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed around the first gate insulating film, gate lines connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance films.
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公开(公告)号：US09825222B2
公开(公告)日：2017-11-21
申请号：US15140189
申请日：2016-04-27
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L45/00 , H01L27/24 , H01L23/528 , G11C13/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/0097 , G11C2213/51 , G11C2213/52 , G11C2213/79 , H01L23/528 , H01L27/2454 , H01L27/2463 , H01L45/1206 , H01L45/124 , H01L45/126 , H01L45/1286 , H01L45/144 , H01L45/1608 , H01L45/1666 , H01L45/1675
摘要： A memory device includes memory elements arranged in two or more rows and two or more columns. Each memory element includes a pillar-shaped insulator layer, a phase change film around an upper portion of the pillar-shaped insulator layer, a lower electrode formed around a lower portion of the pillar-shaped insulator layer and connected to the phase change film, a reset gate insulating film surrounding the phase change film, and a reset gate surrounding the reset gate insulating film. The reset gates are connected to one another in a row direction and a column direction, and are heaters. The phase change films are electrically insulated from the reset gates. A method for producing the memory device is also provided.
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公开(公告)号：US09806163B2
公开(公告)日：2017-10-31
申请号：US15147097
申请日：2016-05-05
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L21/84 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L27/092 , H01L29/06 , H01L21/8238 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/823487 , H01L21/823807 , H01L21/823885 , H01L27/092 , H01L27/0924 , H01L29/0653 , H01L29/66666 , H01L29/7827 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second pillar-shaped silicon layers reside on the first and second fin-shaped silicon layers, respectively. An n-type diffusion layer resides in an upper portion of the first fin-shaped silicon layer and in upper and lower portions of the first pillar-shaped silicon layer. A p-type diffusion layer resides in an upper portion of the second fin-shaped silicon layer and upper and lower portions of the second pillar-shaped silicon layer. First and second gate insulating films and metal gate electrodes are around the first and second pillar-shaped silicon layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped silicon layers.
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