Multiprocessor initialization via firmware configuration

    公开(公告)号:US10564983B2

    公开(公告)日:2020-02-18

    申请号:US15183192

    申请日:2016-06-15

    Applicant: VMware, Inc.

    Abstract: An example method of initializing a plurality of processors in a hardware platform of computing device for use by system software executing on the hardware platform includes: parsing a descriptor table that has been loaded into memory from firmware to identify an original boot protocol for initializing at least one secondary processor of the plurality of processors; creating at least one mailbox structure in the memory associated with the at least one secondary processor; causing the at least one secondary processor to execute secondary processor initialization code stored in the memory, the secondary processor initialization code implementing a mailbox-based boot protocol that uses the at least one mailbox structure to initialize the at least one secondary processor; and modifying the descriptor table to identify the mailbox-based boot protocol for initializing the at least one secondary processor in place of the original boot protocol.

    Method and system to virtualize graphic processing services

    公开(公告)号:US10127628B2

    公开(公告)日:2018-11-13

    申请号:US15439314

    申请日:2017-02-22

    Applicant: VMware, Inc.

    Abstract: Methods and systems configured to virtualize graphic processing services in a virtual machine environment are disclosed. A virtual machine monitor (VMM) may be configured to maintain a virtual machine (VM) based on a host operating system (OS) executing in the system. The VM may contain a virtualized graphics library (vGLib) configured to support a graphic command from an application executing in the VM. The host OS may contain a graphics library (GLib) configured to support the graphic command and utilize a graphics processing unit (GPU) in the system to process the graphic command. Upon receiving the graphic command from the application, the vGLib may be configured to allocate a memory section in the VM to store the graphic command. And the VMM may be further configured to share access to the memory section with the host OS, thereby allowing the host OS to retrieve the graphic command from the memory section and deliver the graphic command to the GLib for processing.

    Implementing pseudo non-masking interrupts behavior using a priority interrupt controller

    公开(公告)号:US09952990B2

    公开(公告)日:2018-04-24

    申请号:US14876845

    申请日:2015-10-07

    Applicant: VMWARE, INC.

    CPC classification number: G06F13/26

    Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling.

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