公开(公告)号：US20200081850A1

公开(公告)日：2020-03-12

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F13/16 ,  G06F12/1045 ,  G06F12/0873 ,  G06F12/1081 ,  G06F9/46

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

公开(公告)号：US09824173B1

公开(公告)日：2017-11-21

申请号：US14852173

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Bennet An ,  Henry E. Styles ,  Sonal Santan ,  Fernando J. Martinez Vallina ,  Pradip K. Jha ,  David A. Knol ,  Sudipto Chakraborty ,  Jeffrey M. Fifield ,  Stephen P. Rozum

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A software development-based compilation flow for circuit design may include executing, using a processor, a makefile including a plurality of rules for hardware implementation. Responsive to executing a first rule of the plurality of rules, a source file including a kernel specified in a high level programming language may be selected; and, an intermediate file specifying a register transfer level implementation of the kernel may be generated using the processor. Responsive to executing a second rule of the plurality of rules, a configuration bitstream for a target integrated circuit may be generated from the intermediate file using the processor. The configuration bitstream includes a compute unit circuit implementation of the kernel.