公开(公告)号：US5787261A

公开(公告)日：1998-07-28

申请号：US563106

申请日：1995-11-27

申请人： Hideki Osaka ,  Akira Yamagiwa ,  Ryoichi Kurihara ,  Masao Inoue

发明人： Hideki Osaka ,  Akira Yamagiwa ,  Ryoichi Kurihara ,  Masao Inoue

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081

摘要： It is an object of the present invention to provide an active-line inserted/withdrawn functional circuit board, a data transfer system and a computer system which systems allow the functional circuit board to be inserted and withdrawn with signal lines remaining in an active state while achieving a high speed data-transfer of a bus, and the reliability to be enhanced by eliminating malfunctions which occur particularly during the insertion of a functional circuit board. The data transfer system or the computer system comprising: a functional circuit board having a functional circuit, a pre-charge resistor and a switching element connected in parallel to an input/output signal path of the functional circuit and a switching control means for controlling the conduction of the switching element through synchronization with a delayed clock signal resulting from delaying a bus clock signal for use in data transfers through the bus by a time shorter than a bus-clock cycle time of the bus clock signal; and a connector provided on an input/output end of the parallel connection of the pre-charge resistor and the switching element, whereby the functional circuit board can be inserted and withdrawn to and from the bus.

摘要翻译： 本发明的目的是提供一种有源线插入/取出功能电路板，数据传输系统和计算机系统，其中系统允许功能电路板被插入和撤回，信号线保持在活动状态，同时 实现总线的高速数据传送，以及通过消除特别是在插入功能电路板期间发生的故障而增强的可靠性。 数据传送系统或计算机系统包括：功能电路板，具有与功能电路的输入/输出信号路径并联连接的功能电路，预充电电阻和开关元件;以及开关控制装置，用于控制功能电路 开关元件通过与延迟总线时钟信号的延迟时钟信号同步地传导，以用于通过总线的数据传输比总线时钟信号的总线时钟周期时间短的时间; 以及设置在预充电电阻器和开关元件的并联连接的输入/输出端上的连接器，由此功能电路板可以从总线插入和拔出。

公开(公告)号：US5627481A

公开(公告)日：1997-05-06

申请号：US596724

申请日：1996-02-05

申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G11C11/401 ,  H03K19/0175 ,  H04B3/02 ,  H04L25/02 ,  H05K1/02 ,  H05K1/14 ,  H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

摘要翻译： 信号发送电路包括一个或多个具有驱动电路和块内传输线的电路块，用于发送由驱动电路产生的信号，一个或多个电路块具有接收电路和块内传输线，用于发送 信号到所述接收电路，以及主块间传输线，用于在两个驱动和接收电路块之间传播信号。 块间​​传输线在一或两端由一个或两个具有与块间传输线本身基本上相同的阻抗的电阻终止。 块内传输线路中的每一个被提供有电阻元件，其电阻等于或接近于通过从块内传输线路的阻抗减去块间传输线路的阻抗的一半导出的值， 降低信号幅度并抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

公开(公告)号：US5497263A

公开(公告)日：1996-03-05

申请号：US117525

申请日：1993-09-07

申请人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

发明人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03H11/26 ,  H03K17/296

CPC分类号： H03K5/133 ,  G06F1/10 ,  H03K2005/00071 ,  H03K2005/00097 ,  H03K2005/00195

摘要： A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

摘要翻译： 一种可变延迟电路，包括延迟装置，每个延迟装置具有连续连接的多个延迟单元，延迟装置的一些延迟单元连接到信号传输线，其中通过激活或者使多个延迟单元激活来控制延迟时间 根据施加到分别为所述多个延迟单元提供的控制输入端子的控制信号。 一种用于向逻辑电路块提供第二时钟信号的时钟信号提供装置，所述时钟信号提供装置具有用于产生第一时钟信号和参考信号的时钟信号发生器和用于调整第一时钟的相位的相位调整装置 信号相位于第一时钟信号和参考信号之间的相位差，并输出相位调整信号作为第二时钟信号，其中相位调整单元包括能够在第一时钟的初始调整中延迟操作的第一可变延迟电路 信号，与第一可变延迟电路串联布置的第二可变延迟电路，用于在初始调整之后执行延迟操作;以及控制电路，用于控制第一和第二可变延迟电路的延迟时间。

公开(公告)号：US4249091A

公开(公告)日：1981-02-03

申请号：US940009

申请日：1978-09-06

申请人： Akira Yamagiwa

发明人： Akira Yamagiwa

IPC分类号： H03K19/086 ,  H03K19/003

CPC分类号： H03K19/086

摘要： A current mode logic circuit (CML) consisting of emitter-coupled transistors, one acting as a reference element and the other as an input element, a regulation transistor for regulating the emitter current of the transistors, a biasing circuit composed of a diode, a Schottky diode and a resistance element connected in series between a V.sub.EE terminal and a V.sub.CC terminal and a biasing transistor, the collector of the biasing transistor being connected through a resistor to V.sub.CC and connected to the base of the reference transistor, the emitter of which being connected through a resistor to V.sub.EE, the bases of the regulation transistor and the biasing transistor being connected to the point between the resistance element and the Schottky diode, so that the emitter current of the transistors and the reference voltage are automatically regulated, whereby CML maintains both the output levels and the input threshold level almost invariant irrespective of changes of transistor characteristics due to temperature and changes in supply voltage, to provide a circuit which is capable of operating on low-power potential and low-amplitude input signal.

摘要翻译： 由发射极耦合晶体管组成的电流模式逻辑电路（CML），一个用作参考元件，另一个用作输入元件，用于调节晶体管的发射极电流的调节晶体管，由二极管组成的偏置电路， 肖特基二极管和串联连接在VEE端子和VCC端子和偏置晶体管之间的电阻元件，偏置晶体管的集电极通过电阻器连接到VCC并连接到参考晶体管的基极，其发射极为 通过电阻器连接到VEE，调节晶体管和偏置晶体管的基极连接到电阻元件和肖特基二极管之间的点，从而自动调节晶体管的发射极电流和参考电压，从而CML保持 输出电平和输入阈值电平几乎不变，与晶体管特性的变化无关 温度和电源电压变化，以提供能够在低功率电位和低幅度输入信号上工作的电路。

公开(公告)号：US07791366B2

公开(公告)日：2010-09-07

申请号：US12116541

申请日：2008-05-07

申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K19/003

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

公开(公告)号：US20090015289A1

公开(公告)日：2009-01-15

申请号：US12116541

申请日：2008-05-07

申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间​​传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

公开(公告)号：US07295034B2

公开(公告)日：2007-11-13

申请号：US11523558

申请日：2006-09-20

申请人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K19/003

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间​​传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

公开(公告)号：US07015717B2

公开(公告)日：2006-03-21

申请号：US10989279

申请日：2004-11-17

申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K19/003

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

公开(公告)号：US06420900B2

公开(公告)日：2002-07-16

申请号：US09891322

申请日：2001-06-27

申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间​​传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

公开(公告)号：US5852365A

公开(公告)日：1998-12-22

申请号：US712554

申请日：1996-09-13

申请人： Nobuo Tamba ,  Mitsugu Kusunoki ,  Takeshi Miyazaki ,  Akira Masaki ,  Akira Yamagiwa

发明人： Nobuo Tamba ,  Mitsugu Kusunoki ,  Takeshi Miyazaki ,  Akira Masaki ,  Akira Yamagiwa

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/082 ,  H03K7/38

CPC分类号： H03K19/1737

摘要： A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.

摘要翻译： 可变逻辑电路包括存储单元，根据存储在存储单元中的数据导通或截止的晶体管，与上述晶体管串联连接并通过输入信号导通或截止的晶体管， 晶体管，其根据上述晶体管的导通状态产生电压，以及根据选择信号将导通或不导通所产生的电压的输出装置输出到输出端。