摘要:
A laminated balun transformer subminiaturized with a transmission line length reduced below λ/4 without any variation of characteristics. The laminated balun transformer includes a first strip line having one end inputted to a unbalanced signal; a second strip line having connected to the first strip line; a third strip line formed in parallel with the first strip line and connected to a ground and connected to the external electrode for a first balanced signal; a fourth strip line formed in parallel with the second strip line and connected to the external electrode for a ground and the external electrode for a second balanced signal; and a capacitance forming electrode formed in parallel with a portion of the opened end of the second strip line and connected to the external electrode for the unbalanced signal.
摘要:
A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.
摘要:
A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.
摘要:
A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.
摘要:
A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electrodes and the second polarity external electrodes are two or more, respectively, and are identical to each other, and a total number of the multilayer capacitor devices in the multilayer capacitor array is identical to the number of the first polarity external electrodes.
摘要:
A multilayer chip capacitor includes a capacitor body, a plurality of internal electrodes, and a plurality of external electrodes. The capacitor body is formed of a ceramic sintered product and has first and second side surfaces facing each other. The plurality of internal electrodes each of which has two leads extending to the first and second side surfaces of the capacitor body, respectively, are arranged such that the internal electrodes with one polarity and the internal electrodes with the other polarity are alternately stacked inside the capacitor body. The plurality of external electrodes are formed on the first and second side surfaces of the capacitor body along a stacked direction of the internal electrodes such that the external electrodes with one polarity and the external electrodes with the other polarity are alternately arranged on each of the first and second side surfaces, and are connected to the leads.
摘要:
An integrated multilayer chip capacitor module including: plurality of multilayer chip capacitors arranged close to one another and co-planar with one another; and a capacitor support accommodating the multilayer chip capacitors, wherein each of the multilayer chip capacitors includes a rectangular parallelepiped capacitor body and a plurality of first and second external electrodes formed on at least two sides of the capacitor body, and the external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitor in the capacitor support are electrically connected to each other by a conductive adhesive material.
摘要:
A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad. The first via is disposed adjacent to the third pad relative to a central line of the first pad, the second via is disposed adjacent to the third pad relative to a central line of the second pad, one or more of the third vias are disposed adjacent to the first via relative to a central line of the third pad, and the rest of the third vias are disposed adjacent to the second via relative to the central line of the third pad.
摘要:
There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.
摘要:
A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.