公开(公告)号：US07043045B2

公开(公告)日：2006-05-09

申请号：US10410265

申请日：2003-04-10

申请人： Osamu Takahashi

发明人： Osamu Takahashi

IPC分类号： H04R25/00

CPC分类号： H04R7/18

摘要： An edge damper frame 18b is disposed in between a part of an outer peripheral surface 20a of a frame-cover 20 and a leveling surface 14c-1 of a frame 14. A slope 18e of a diaphragm 15 is extended from the edge damper frame 18b toward the frame 14 and provided alongside an outer side surface 14c-2 of a convex portion 14c of the frame 14.

摘要翻译： 边缘阻尼器框架18b设置在框架盖20的外周表面20a的一部分和框架14的调平表面14c-1之间。 隔膜15的斜面18e从边缘阻尼器框架18b朝向框架14延伸，并且设置在框架14的凸部14c的外侧表面14c-2的旁边。

公开(公告)号：US20060083101A1

公开(公告)日：2006-04-20

申请号：US10965627

申请日：2004-10-14

申请人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

发明人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

IPC分类号： G11C8/00

CPC分类号： G11C8/06

摘要： An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

公开(公告)号：US20050264324A1

公开(公告)日：2005-12-01

申请号：US10852863

申请日：2004-05-25

申请人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

发明人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

IPC分类号： G11C11/419 ,  G11C7/06 ,  H03F3/45 ,  H03K3/012 ,  H03K3/356

CPC分类号： H03K3/012 ,  G11C7/065 ,  H03K3/356139

摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

摘要翻译： 用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。 在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少 通过位线晶体管的动作将中间节点处的电压拉低。 在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

公开(公告)号：US06963227B2

公开(公告)日：2005-11-08

申请号：US10295424

申请日：2002-11-15

申请人： Hiroaki Murakami ,  Shoji Onishi ,  Osamu Takahashi

发明人： Hiroaki Murakami ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： H03K19/0944 ,  H03K19/096 ,  H03K19/094

CPC分类号： H03K19/096

摘要： A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously.

摘要翻译： 多米诺骨牌电路配置包括耦合到放电晶体管的预充电晶体管，其中预充电晶体管和放电晶体管不同时接通。

公开(公告)号：US20050231563A1

公开(公告)日：2005-10-20

申请号：US11019665

申请日：2004-12-23

申请人： Takeshi Fujishiro ,  Osamu Takahashi

发明人： Takeshi Fujishiro ,  Osamu Takahashi

IPC分类号： B41J2/175 ,  B41J2/045

CPC分类号： F16K31/1266 ,  B41J2/17596 ,  G05D16/0647 ,  G05D16/0677 ,  Y10T137/783

摘要： A valve device has a pressure chamber, which is connected to a liquid inlet and a liquid outlet and retains liquid, and a pressure regulator decreasing the pressure in the pressure chamber to a predetermined level. The pressure regulator has a pressure receiving member. When the pressure in the pressure chamber becomes lower than the predetermined level, the pressure receiving member is elastically deformed in an inward direction of the pressure chamber. The pressure regulator generates actuation force greater than the pressing force produced by the elastic deformation of the pressure receiving member. The pressure regulator is configured to be opened by the actuation force. When the pressure regulator is open, a fluid supply from the liquid inlet to the pressure chamber is permitted. It is thus possible to minimize the valve device.

摘要翻译： 阀装置具有连接到液体入口和液体出口并保持液体的压力室，以及将压力室中的压力降低到预定水平的压力调节器。 压力调节器具有受压构件。 当压力室中的压力变得低于预定水平时，受压构件在压力室的内部方向上弹性变形。 压力调节器产生大于由受压构件的弹性变形产生的按压力的致动力。 压力调节器构造成通过致动力打开。 当压力调节器打开时，允许从液体入口到压力室的流体供应。 因此可以使阀装置最小化。

公开(公告)号：US06944088B2

公开(公告)日：2005-09-13

申请号：US10262500

申请日：2002-09-30

申请人： Toru Asano ,  Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi

发明人： Toru Asano ,  Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi

IPC分类号： G06F9/355 ,  G06F12/08 ,  G11C8/10 ,  G11C8/00

CPC分类号： G06F9/355 ,  G06F12/0895 ,  G11C8/10

摘要： A sum decoder is disclosed including multiple sum predecoders, a carry generator, and multiple rotate logic units. Each sum predecoder receives multiple bit pairs of non-overlapping segments of a first and second address signal, and produces an input signal dependent upon the bit pairs. The carry generator receives a lower-ordered portion of the first and second address signals, and generates multiple carry signals each corresponding to a different one of the sum predecoders. Each rotate logic unit receives the input signal produced by a corresponding sum predecoders and a corresponding one of the carry signals, rotates the bits of the input signal dependent upon the carry signal, and produces either the input signal or the rotated input signal as an output signal. A memory is described including the sum decoder, a final decode block, and a data array. The final decode block performs logical operations on the output signals of the sum decoder to produce selection signals. Each of the selection signals activates a word line of the data array. A method is disclosed for producing signals for accessing a memory. Highest ordered portions of the first and second address signals are divided into multiple non-overlapping segments. An input signal (i.e., an I term) is generated for each of the segments, as is a carry signal. For each of the segments, when the corresponding carry signal is set, the corresponding I term is rotated one bit position. The I terms are produced as the signals.

摘要翻译： 公开了一种和解解码器，其包括多个和预测解码器，进位发生器和多个旋转逻辑单元。 每个和预解码器接收第一和第二地址信号的非重叠段的多个比特对，并且根据比特对产生输入信号。 进位发生器接收第一和第二地址信号的低阶部分，并且产生每个对应于预测解码器中的不同一个的多个进位信号。 每个旋转逻辑单元接收由相应的和预测码器和相应的一个进位信号产生的输入信号，根据进位信号旋转输入信号的位，并产生输入信号或旋转的输入信号作为输出 信号。 描述包括和解码器，最终解码块和数据阵列的存储器。 最终解码块对和解码器的输出信号执行逻辑运算以产生选择信号。 每个选择信号激活数据阵列的字线。 公开了一种用于产生访问存储器的信号的方法。 第一和第二地址信号的最高有序部分被分成多个非重叠段。 对于每个段产生输入信号（即I项），进位信号也是如此。 对于每个段，当相应的进位信号被设置时，对应的I项被旋转一位位置。 我的条款是作为信号产生的。

公开(公告)号：US20050162708A1

公开(公告)日：2005-07-28

申请号：US11041255

申请日：2005-01-25

申请人： Osamu Takahashi

发明人： Osamu Takahashi

IPC分类号： H04N1/19 ,  H04N1/393 ,  H04N1/40

CPC分类号： H04N1/40068

摘要： The image reading apparatus comprising an image sensor with plurality of reading devices one-dimensionally aligned in a main scanning direction allows reducing memory space necessary for image reduction process. Pixel signals in each channel read by a line image sensor are converted into pixel data in AFE, valid pixel data are captured therefrom, and then inputted into a reduction process unit. The reduction process unit skips pixel data sequentially inputted therein with predetermined intervals based on preset data reduction rate. Subsequently, pixel data after reduction process, that is only unskipped pixel data, are written into a memory via writing unit and memory control unit.

摘要翻译： 包括具有在主扫描方向上一维排列的多个读取装置的图像传感器的图像读取装置允许减少图像缩小处理所需的存储空间。 通过线图像传感器读取的每个通道中的像素信号被转换成AFE中的像素数据，从其中捕获有效像素数据，然后输入到缩小处理单元。 缩小处理单元基于预设的数据缩小率，以预定间隔跳过依次输入的像素数据。 随后，经过写入单元和存储器控制单元，将还原处理后的像素数据（即只有非贴片像素数据）写入存储器。

公开(公告)号：US06872059B2

公开(公告)日：2005-03-29

申请号：US10242547

申请日：2002-09-12

申请人： Osamu Takahashi ,  Masatoshi Moteki

发明人： Osamu Takahashi ,  Masatoshi Moteki

IPC分类号： F04C5/00 ,  F04B43/12 ,  F04B43/08

CPC分类号： F04B43/1269

摘要： A liquid discharger 1A has a base 2A where a resilient tube 100 is disposed in a tube guide groove 211A. A retainer 4A is rotatably provided at the base 2A, with a plurality of balls 5 being mounted at the retainer 4A so that the balls can roll. The cross sectional shape of a surface 211 defining the tube guide groove 211A that contacts the tube 100 has an arc shape formed concentrically with the balls 5. The balls 5, which are held by the retainer 4A, roll on the tube 100 while pressing and squashing a portion of the tube 100 as a rotor 3A rotates in order to discharge liquid inside the tube 100.

摘要翻译： 排液器1A具有基部2A，其中弹性管100设置在管引导槽211A中。 保持架4A可旋转地设置在基座2A处，多个球5安装在保持器4A上，使得球可以滚动。 限定与管100接触的导向槽211A的表面211的横截面形状具有与滚珠5同心形成的弧形。由保持器4A保持的滚珠5在压制时在管100上滚动， 当转子3A旋转时挤压管100的一部分以便排出管100内的液体。

公开(公告)号：US06717882B1

公开(公告)日：2004-04-06

申请号：US10273590

申请日：2002-10-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.

摘要翻译： 提供用于多端口存储器中的用于数据读出的改进的单元电路。 多端口存储器存储写入数据信号。 电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。 每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。 每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

公开(公告)号：US06600959B1

公开(公告)日：2003-07-29

申请号：US09498934

申请日：2000-02-04

申请人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

发明人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

IPC分类号： G05B1918

CPC分类号： H03K17/693 ,  H03K5/06

摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.

摘要翻译： 在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。 该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。