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31.
公开(公告)号:US20220173708A1
公开(公告)日:2022-06-02
申请号:US17503710
申请日:2021-10-18
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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公开(公告)号:US11239801B2
公开(公告)日:2022-02-01
申请号:US15931236
申请日:2020-05-13
Applicant: pSemi Corporation
Inventor: Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号:US20210143779A1
公开(公告)日:2021-05-13
申请号:US16953141
申请日:2020-11-19
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
IPC: H03F3/195 , H03F1/02 , H03H11/28 , H04B1/16 , H03H7/38 , H03F1/22 , H03F1/56 , H03F3/193 , H03F3/72 , H04B1/00
Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
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34.
公开(公告)号:US10862441B2
公开(公告)日:2020-12-08
申请号:US16664646
申请日:2019-10-25
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
IPC: H03F3/191 , H03F1/22 , H03F3/195 , H03F1/02 , H03H11/28 , H04B1/16 , H03H7/38 , H03F1/56 , H03F3/193 , H03F3/72 , H04B1/00
Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
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公开(公告)号:US20200321935A1
公开(公告)日:2020-10-08
申请号:US16852275
申请日:2020-04-17
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Ke Li , James Francis McElwee , Tero Tapio Ranta , Kevin Roberts , Chih-Chieh Cheng
Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.
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公开(公告)号:US10700650B1
公开(公告)日:2020-06-30
申请号:US16242883
申请日:2019-01-08
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
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37.
公开(公告)号:US20190020322A1
公开(公告)日:2019-01-17
申请号:US16046962
申请日:2018-07-26
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
CPC classification number: H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/3052 , H03G2201/504
Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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38.
公开(公告)号:US10038418B1
公开(公告)日:2018-07-31
申请号:US15479173
申请日:2017-04-04
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
CPC classification number: H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/3052 , H03G2201/504
Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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公开(公告)号:US12237821B2
公开(公告)日:2025-02-25
申请号:US18492357
申请日:2023-10-23
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Ke Li , James Francis McElwee , Tero Tapio Ranta , Kevin Roberts , Chih-Chieh Cheng
IPC: H04B1/04 , H01B1/00 , H03H7/01 , H03H7/38 , H04B1/00 , H04B1/40 , H04W72/0453 , H04W88/06 , H04L5/00 , H04W28/06
Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.
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公开(公告)号:US12218637B2
公开(公告)日:2025-02-04
申请号:US18534153
申请日:2023-12-08
Applicant: pSemi Corporation
Inventor: Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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