公开(公告)号：US20140040536A1

公开(公告)日：2014-02-06

申请号：US13955454

申请日：2013-07-31

申请人： GENUSION INC.

发明人： Moriyoshi NAKASHIMA

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F21/62 ,  G06F21/78 ,  G06F2212/1052 ,  G06F2212/7205 ,  G06F2221/2143

摘要： A storage medium using a nonvolatile semiconductor storage device for erasing data with certainty on a file-by-file basis and preventing an inadvertent file leak as much as possible is provided. A file erasing method includes (a) reading data other than data in a file which is a target of erase from an erase block having the file as the target of erase recorded therein; (b) writing the read data other than the data in the file which is the target of erase to another erase block; and (c) erasing all the data in the erase block in which the file as the target of erase is recorded.

摘要翻译： 提供一种使用非易失性半导体存储装置的存储介质，用于逐个擦除数据，并且尽可能地防止无意的文件泄漏。 文件擦除方法包括（a）从作为其中记录的擦除目标的文件的擦除块读取作为擦除目标的文件中的数据以外的数据; （b）将作为擦除对象的文件中的数据以外的读取数据写入另一擦除块; 和（c）擦除作为擦除目标的文件被记录的擦除块中的所有数据。

公开(公告)号：US20130265823A1

公开(公告)日：2013-10-10

申请号：US13855902

申请日：2013-04-03

申请人： GENUSION, INC.

发明人： Natsuo AJIKA ,  Taku OGURA ,  Masaaki MIHARA

IPC分类号： G11C16/34

CPC分类号： G11C16/3431 ,  G11C11/5628 ,  G11C11/5642

摘要： A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.

摘要翻译： 提供了一种非易失性半导体存储器件，其包括：具有源极，漏极，栅极和电荷存储层的P型存储单元晶体管; 以及控制电路，其中在P型存储单元晶体管的阈值大于或等于第一值（Vr）且小于或等于第二值（Vrd）的情况下，执行程序操作 将电子注入电荷存储层。

公开(公告)号：US20130070542A1

公开(公告)日：2013-03-21

申请号：US13421255

申请日：2012-03-15

申请人： Koji Shinbayashi

发明人： Koji Shinbayashi

IPC分类号： G05F1/10 ,  G11C7/00

CPC分类号： G05F1/10 ,  G11C5/145 ,  G11C5/147 ,  G11C7/00 ,  G11C16/30

摘要： A replica circuit includes: a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor; a second current path including a first conductivity type fourth transistor configured so that current equivalent to a current flowing through the first transistor flows through the fourth transistor, and a second conductivity type fifth transistor configured so that current equivalent to a current flowing through the third transistor flows through the fifth transistor, the fourth transistor and the fifth transistor being connected in series; a second conductivity type sixth transistor configured so a current equivalent to a current flowing through the third transistor flows through the sixth transistor; a first control configured to supply a reference voltage to the drain of the first transistor; and a second control configured to supply the reference voltage to the drain of the fourth transistor.

摘要翻译： 复制电路包括：第一导电类型的第一晶体管; 包括第一导电类型的第二晶体管和第二导电类型的第三晶体管的第一电流路径; 第二电流路径，包括第一导电类型的第四晶体管，其被配置为使得等于流过第一晶体管的电流的电流流过第四晶体管;以及第二导电类型第五晶体管，被配置为使得流过第三晶体管的电流的电流 流过第五晶体管，第四晶体管和第五晶体管串联连接; 第二导电型第六晶体管被配置为使流过第三晶体管的电流等效的电流流过第六晶体管; 第一控制器，被配置为向所述第一晶体管的漏极提供参考电压; 以及第二控制，被配置为将参考电压提供给第四晶体管的漏极。

公开(公告)号：US20120112265A1

公开(公告)日：2012-05-10

申请号：US13350703

申请日：2012-01-13

申请人： Natsuo AJIKA ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo AJIKA ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0441 ,  G11C16/0491 ,  H01L21/26586 ,  H01L29/792

摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

摘要翻译： 非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部 所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层， 形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散 肋骨中的结构是不对称的。

公开(公告)号：US20100149875A1

公开(公告)日：2010-06-17

申请号：US12714750

申请日：2010-03-01

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20090090961A1

公开(公告)日：2009-04-09

申请号：US12246193

申请日：2008-10-06

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0441 ,  G11C16/0491 ,  H01L21/26586 ,  H01L29/792

摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

摘要翻译： 非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部 所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层， 形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散 肋骨中的结构是不对称的。

公开(公告)号：US20090073740A1

公开(公告)日：2009-03-19

申请号：US11776491

申请日：2007-07-11

申请人： TAKU OGURA ,  MASAAKI MIHARA ,  YOSHIKI KAWAJIRI

发明人： TAKU OGURA ,  MASAAKI MIHARA ,  YOSHIKI KAWAJIRI

IPC分类号： G11C5/06 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C14/00 ,  G11C14/0063

摘要： An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters comprising memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

摘要翻译： 本发明的目的是提供一种可以具有宽的读取余量的可重写非易失性存储单元，并且可以通过改变Vcc的电平来控制字线和位线。 作为解决方案，触发器通过包括存储器晶体管的逆变器的交叉（环路）连接形成，该存储器晶体管可以通过电荷注入到晶体管的侧隔板中来控制阈值电压。 在向一个存储晶体管写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极，并且通过另一侧反相器的负载晶体管将高电压提供给存储晶体管的栅极。 在擦除写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极。

公开(公告)号：US07420206B2

公开(公告)日：2008-09-02

申请号：US11456913

申请日：2006-07-12

申请人： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

发明人： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC分类号： H01L29/10

CPC分类号： H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US20080186766A1

公开(公告)日：2008-08-07

申请号：US12025566

申请日：2008-02-04

申请人： Taku Ogura ,  Natsuo Ajika

发明人： Taku Ogura ,  Natsuo Ajika

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：第一N型阱; 多个P型非易失性存储单元，被布置成矩阵形成在N型阱中; 多个子位线，每个子位线连接到矩阵的相应列中的P型非易失性存储单元的漏极; 第一个P型井; 和多个N型选择晶体管，所述选择晶体管中的每一个选择性地将相应的一个子位线连接到相应的一个主位线。