公开(公告)号：US20220244913A1

公开(公告)日：2022-08-04

申请号：US17163556

申请日：2021-01-31

Applicant: Redpine Signals, Inc.

Inventor： Martin KRAEMER ,  Ryan BOESCH ,  Wei Xiong

IPC: G06F7/53

Abstract: A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.

公开(公告)号：US20220209788A1

公开(公告)日：2022-06-30

申请号：US17139945

申请日：2020-12-31

Applicant: Redpine Signals, Inc.

Inventor： Martin KRAEMER ,  Ryan BOESCH ,  Wei XIONG

IPC: H03M3/04 ,  G06F7/544

Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

公开(公告)号：US20220206753A1

公开(公告)日：2022-06-30

申请号：US17139242

申请日：2020-12-31

Applicant: Redpine Signals, Inc.

Inventor： Ryan BOESCH ,  Martin KRAEMER ,  Wei XIONG

IPC: G06F7/544

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

公开(公告)号：US20220100255A1

公开(公告)日：2022-03-31

申请号：US17461923

申请日：2021-08-30

Applicant: Redpine Signals, Inc.

Inventor： Subba Reddy KALLAM ,  Venkat MATTELA ,  Aravinth Kumar AYYAPPANNAIR RADHADEVI ,  Sesha Sairam Regulagadda

IPC: G06F1/3234 ,  G06F15/80 ,  H03M1/80 ,  G06F1/06 ,  H03M1/12 ,  G06F7/544 ,  H03M1/66

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

公开(公告)号：US20190239068A1

公开(公告)日：2019-08-01

申请号：US15883092

申请日：2018-01-29

Applicant: Redpine Signals, Inc.

Inventor： Sriram MUDULODU ,  Venkat MATTELA

IPC: H04W12/06 ,  H04W12/04 ,  H04L9/32

Abstract: An IoT device has a public device identifier and a private device identifier, where the public device identifier is publicly available and the private device identifier is secret but kept in a secure device database as a tuple. A registration request containing encrypted credentials comprising at least a private identifier and optionally a public identifier is sent from the IoT device to an association server in communication with a device database having an association between IoT public identifier and a corresponding IoT private identifier. The association server which receives the registration request and encrypted credentials responds with a registration acknowledgement when the decrypted credentials match the tuple in the device database, or forwards the request to a registration server when it does not. The requesting IoT device receives an acknowledgement and is thereafter able to join the wireless network.

公开(公告)号：US09888096B1

公开(公告)日：2018-02-06

申请号：US15485492

申请日：2017-04-12

Applicant: Redpine Signals, Inc.

Inventor： Govardhan Mattela

IPC: H04B1/38 ,  H04M1/00 ,  H04L29/06 ,  H04W72/04 ,  H04W4/00 ,  H04W84/12 ,  H04W88/06

CPC classification number: H04L69/18 ,  H04B1/38 ,  H04W4/80 ,  H04W72/0406 ,  H04W72/1215 ,  H04W84/005 ,  H04W84/12 ,  H04W88/06

Abstract: A multi-protocol transceiver provides a plurality of RF front ends, each responsive to a particular protocol and frequency, a common set of analog/digital converters, a baseband processor which receives and demodulates and also modulates and transmits baseband wireless packets for mixing to a carrier frequency by each RF front end. A timing controller allocates intervals of time for a first protocol such as WAVE protocol, and also allocates exclusive intervals of time for a second protocol such as Bluetooth.

公开(公告)号：US08399849B1

公开(公告)日：2013-03-19

申请号：US12538138

申请日：2009-08-08

Applicant: Mahadevan Krishnan ,  Mahmud Vahdat Roshan ,  Paul Choon Keat Lee ,  Rajdeep Singh Rawat ,  Stuart Victor Springham

Inventor： Mahadevan Krishnan ,  Mahmud Vahdat Roshan ,  Paul Choon Keat Lee ,  Rajdeep Singh Rawat ,  Stuart Victor Springham

IPC: G01T5/00 ,  G01T1/00

CPC classification number: G01T3/06

Abstract: An activation detector for fast-neutrons has a yttrium target exposed to a neutron source. Fast-neutrons which have energy in excess of 1 MeV (above a threshold energy level) generate gamma rays from a nuclear reaction with the yttrium, the gamma rays having an energy level of 908.96 keV, and the resultant gamma rays are coupled to a scintillator which generates an optical response, the optical response of the scintillator is coupled to a photomultiplier tube which generates an electrical response. The number of counts from the photomultiplier tube provides an accurate indication of the fast-neutron flux, and the detector is exclusively sensitive to fast-neutrons with an energy level over 1 MeV, thereby providing a fast-neutron detector which does not require calibration or the setting of a threshold.

Abstract translation: 用于快中子的激活检测器具有暴露于中子源的钇靶。 具有超过1MeV（高于阈值能级）的能量的快中子产生与钇的核反应的伽马射线，伽马射线具有908.96keV的能级，并且所得到的伽马射线与闪烁体 其产生光学响应，闪烁体的光学响应耦合到产生电响应的光电倍增管。 来自光电倍增管的计数提供了快中子通量的精确指示，检测器对能量水平超过1 MeV的快中子是非常敏感的，从而提供不需要校准的快中子检测器 设置阈值。

公开(公告)号：US08259786B2

公开(公告)日：2012-09-04

申请号：US12368431

申请日：2009-02-10

Applicant: Partha Sarathy Murali ,  Kashiviswanath Nethi ,  Karthik Vaidyanathan ,  Sundaram Vanka

Inventor： Partha Sarathy Murali ,  Kashiviswanath Nethi ,  Karthik Vaidyanathan ,  Sundaram Vanka

IPC: H03H7/30

CPC classification number: H04L27/2647 ,  H04L25/022 ,  H04L25/03159

Abstract: A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.

Abstract translation: 具有有限脉冲响应（FIR）的信道平滑滤波器具有控制器，其以这样的方式从FFT存储器中读取并行取样数据，以产生偶函数，该样本数据应用于伴有前置码符号的前同步码均衡器， 零，所述前导码输出耦合到三个滤波器处理器，每个滤波器处理器具有四个滤波器引擎，其输出相加，所述信道平滑滤波器产生寄存器输出，耦合到具有作为输入的加法器的寄存器输入：第一滤波器处理器被移位 由四个，第二个滤波器处理器移位两个，第三个滤波器处理器和寄存器输出。 边缘滤波器和中央滤波器的系数以零符号移位（ZSS）格式提供，并且通过使用规范有符号数字（CSD）算法选择系数，通道平滑FIR滤波器不需要乘法器。

公开(公告)号：US08223906B2

公开(公告)日：2012-07-17

申请号：US12197234

申请日：2008-08-23

Applicant: Prem Kiran Nerella ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

Inventor： Prem Kiran Nerella ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

IPC: H04B1/10 ,  H04L27/28

CPC classification number: H04L27/2647 ,  H04L27/2626

Abstract: A transmit filter for a stream of OFDM symbols has a remapper, Infinite Impulse Response (IIR) filter and a controller, the transmit filter operating on a stream of OFDM symbols. The transmit filter accepts symbols to be transmitted, the re-mapper re-orders them, the IIR filters the re-ordered stream, and a controller provides an output by rearranging the filtered symbols. The incoming symbol stream contains a series of symbols, each followed by a guard interval, where each guard interval has a first Tg symbol interval, and a second Tg symbol interval, the remapper generating a re-ordered stream having a first Tg symbol interval, a second Tg symbol interval and the symbol, the output of the IIR filter thereby generating a filtered first Tg symbol, a filtered second Tg symbol, and a filtered symbol, and the controller forms the transmit output by discarding the filtered first Tg symbol and outputting, in sequence, the filtered second Tg symbol, the filtered symbol, and a copy of the filtered second Tg symbol. The filtered second Tg symbol may be saved into a local buffer at the time it is initially output for use following the current symbol.

Abstract translation: 用于OFDM符号流的发射滤波器具有再映射器，无限脉冲响应（IIR）滤波器和控制器，所述发射滤波器在OFDM符号流上操作。 发送过滤器接受要发送的符号，重新映射器重新命令它们，IIR对重新排序的流进行滤波，并且控制器通过重排排序的滤波符号来提供输出。 输入符号流包含一系列符号，每个符号后面是保护间隔，其中每个保护间隔具有第一Tg符号间隔和第二Tg符号间隔，再生映射器产生具有第一Tg符号间隔的重排序流， 第二Tg符号间隔和符号，IIR滤波器的输出，从而产生滤波后的第一Tg符号，滤波后的第二Tg符号和滤波符号，并且控制器通过丢弃滤波后的第一Tg符号并输出 按照顺序，滤波后的第二Tg符号，滤波后的符号和滤波的第二Tg符号的副本。 经滤波的第二Tg符号可以在其最初输出之后被保存到本地缓冲器中以便在当前符号之后使用。

公开(公告)号：US08149965B2

公开(公告)日：2012-04-03

申请号：US12211337

申请日：2008-09-16

Applicant: Dharani Naga Sailaja Sankabathula ,  Partha Sarathy Murali ,  Logeshwaran Vijayan ,  Nagaraja Reddy Anakala

Inventor： Dharani Naga Sailaja Sankabathula ,  Partha Sarathy Murali ,  Logeshwaran Vijayan ,  Nagaraja Reddy Anakala

IPC: H04L27/08 ,  H03K9/00

CPC classification number: H04L1/206 ,  H04L27/0006 ,  H04L27/2647

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract translation: 分组检测控制器接受来自AGC控制器的输入，其指示增加的信号能量的存在以及AGC处理的完成，并且产生用于暂停AGC过程的输出。 分组检测控制器还接收多个IQ接收机流并且形成单个流以供分组检测器使用，该分组检测器可以由指示信噪比是高于还是低于特定阈值的SNR_MODE控制，以及表示PD_RESET信号的PD_RESET信号 不会发生数据包检测。 控制器还接收一个指示分组检测完成的PACKET_DET信号。 如果产生分组检测，分组检测控制器检查输入的接收机流并暂停AGC处理，或者如果需要AGC过程则暂停分组检测器。