公开(公告)号：US20110061096A1

公开(公告)日：2011-03-10

申请号：US12943213

申请日：2010-11-10

申请人： FABRICE JOGAND-COULOMB

发明人： FABRICE JOGAND-COULOMB

IPC分类号： G06F12/14

CPC分类号： H04L63/10 ,  G06F21/10 ,  G06F21/78 ,  G06F2221/2135

摘要： Method for utilizing digital content is provided. The method includes controlling a throughput rate for utilizing the digital content by an accessing system, where the throughput rate is associated with information related to the digital content and is stored as a file. The throughput rate is controlled by a storage system that is operationally coupled to the accessing system.

公开(公告)号：US07904780B2

公开(公告)日：2011-03-08

申请号：US11556632

申请日：2006-11-03

申请人： Yigal Brandman

发明人： Yigal Brandman

IPC分类号： H03M13/00

CPC分类号： G06F11/1068 ,  G06F11/1072

摘要： Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that is subsequently used in decoding a second page.

摘要翻译： 数据存储在非易失性存储器中，使得存储在相同存储单元中的不同数据页面根据不同的编码方案进行编码。 根据其编码方案对第一页面进行解码，并且基于随后在第二页面的解码中使用的第一页面的解码来提供输出。

公开(公告)号：US07903014B1

公开(公告)日：2011-03-08

申请号：US12645200

申请日：2009-12-22

申请人： Feng Pan

发明人： Feng Pan

IPC分类号： H03M1/66

CPC分类号： H03M1/0612 ,  H03M1/785

摘要： A circuit and corresponding method are presented for generating an analog voltage from a digital input value is presented. An digital to analog conversion circuit, which is connected between a node and ground, receives an N-bit digital input value and generate from it a corresponding analog voltage. The node receives an input voltage provided by an op-amp connected to receive a reference voltage. The circuit also includes a variable resistance connected between the first node and ground in parallel with the digital to analog conversion circuit. The variable resistance is also connected to receive one or more of the digital input value and the value of the variable resistance is dependent upon the digital input values such that the combined current drawn from the first node by the variable resistance and the digital to analog conversion circuit is essentially constant during operation.

摘要翻译： 提出了一种用于从数字输入值产生模拟电压的电路和相应方法。 连接在节点和地之间的数模转换电路接收N位数字输入值并从中产生相应的模拟电压。 节点接收由连接的运算放大器提供的输入电压以接收参考电压。 该电路还包括与数模转换电路并联连接在第一节点和地之间的可变电阻。 可变电阻还被连接以接收数字输入值中的一个或多个，并且可变电阻的值取决于数字输入值，使得从第一节点通过可变电阻和数模转换得到的组合电流 电路在运行期间基本上是恒定的。

公开(公告)号：US07890724B2

公开(公告)日：2011-02-15

申请号：US11618526

申请日：2006-12-29

申请人： Ronald LaPedis ,  Arrigo Triulzi

发明人： Ronald LaPedis ,  Arrigo Triulzi

IPC分类号： G06F12/00

CPC分类号： G06F9/445 ,  G06F12/1433 ,  G06F21/53 ,  G06F2221/2141 ,  G06F2221/2149

摘要： System for executing software application is provided. The system includes a non-volatile memory device that includes a plurality of memory cells, wherein a read only segment of a plurality of memory cells stores: (a) code for a micro-operating system for running a virtual engine; (b) code for the virtual engine that provides a virtual environment, independent of a host operating system; (c) code for a virtual operating system that is executed in the virtual environment; and (d) code for a software application, wherein the code for the software application can be executed in different host system platforms in the virtual environment.

摘要翻译： 提供执行软件应用程序的系统。 该系统包括包括多个存储单元的非易失性存储器件，其中多个存储器单元中的只读段存储：（a）用于运行虚拟引擎的微操作系统的代码; （b）提供独立于主机操作系统的虚拟环境的虚拟引擎的代码; （c）在虚拟环境中执行的虚拟操作系统的代码; 和（d）用于软件应用程序的代码，其中用于软件应用程序的代码可以在虚拟环境中的不同主机系统平台中执行。

公开(公告)号：US07889590B2

公开(公告)日：2011-02-15

申请号：US12611280

申请日：2009-11-03

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C8/00

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities.

公开(公告)号：US07885119B2

公开(公告)日：2011-02-08

申请号：US11459001

申请日：2006-07-20

申请人： Yan Li

发明人： Yan Li

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C16/3418

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 为了补偿该耦合，给定存储器单元的读取或编程过程可以考虑相邻存储器单元的编程状态。 为了确定是否需要补偿，可以执行包括感测关于相邻存储器单元的编程状态的信息（例如，在相邻位线或其他位置上）的处理。

公开(公告)号：US07875996B2

公开(公告)日：2011-01-25

申请号：US12005144

申请日：2007-12-21

申请人： Daniel P. Nguyen ,  Steve X. Chi ,  Po-Shen Lai

发明人： Daniel P. Nguyen ,  Steve X. Chi ,  Po-Shen Lai

IPC分类号： H02J1/00 ,  H02J3/00

CPC分类号： H02M1/36 ,  G11C16/30 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16 ,  Y10T307/696

摘要： An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

摘要翻译： 电子产品包括专用半导体芯片（ASIC）器件，其在其电路中包括被配置为耦合到可选外部电容的线性调节器模块和被配置为耦合到电子产品的内部电容的无电容调节器模块。 ASIC设备的控制逻辑响应于调节器选择信号，用于选择线性调节器模块和无限幅调节器模块之一，以用于为ASIC设备供电。 控制逻辑可以在某些操作时间内选择线性调节器模块，并在其他操作时间内选择无限幅调节器模块。

公开(公告)号：US07873803B2

公开(公告)日：2011-01-18

申请号：US11861146

申请日：2007-09-25

申请人： Steven S. Cheng

发明人： Steven S. Cheng

IPC分类号： G06F12/00

CPC分类号： G06F11/1666 ,  G06F11/20 ,  G11C29/74 ,  G11C29/765

摘要： A nonvolatile memory array includes two or more devices, each device containing data that is scrambled using a different scrambling scheme. When the same data is provided and stored in both devices, different data patterns occur in each device, so that if one of the patterns causes data pattern induced errors, the original data can be recreated from another copy that does not share the same data pattern.

摘要翻译： 非易失性存储器阵列包括两个或更多个器件，每个器件包含使用不同的加扰方案加扰的数据。 当相同的数据被提供并存储在两个设备中时，在每个设备中出现不同的数据模式，使得如果其中一个模式导致数据模式引起的错误，则可以从不共享相同数据模式的另一个副本重新创建原始数据 。

公开(公告)号：US20100332943A1

公开(公告)日：2010-12-30

申请号：US12494210

申请日：2009-06-29

申请人： MANUEL ANTONIO D'ABREU ,  STEPHEN SKALA

发明人： MANUEL ANTONIO D'ABREU ,  STEPHEN SKALA

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C16/10 ,  G06F11/1068 ,  G11C16/3431

摘要： A method and device for selectively refreshing a region of a non-volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage device for a first region of a non-volatile memory, the first region including a least recently accessed region of a memory array within the data storage device. The method also includes selectively refreshing the first region based on a comparison of a difference between the time stamp received from the host device and the first time stamp as compared to a threshold, where the threshold is adjusted based on a first error count corresponding to a number of errors detected by an error correction code (ECC) engine with respect to data retrieved from the first region.

摘要翻译： 公开了一种用于有选择地刷新数据存储装置的非易失性存储器的区域的方法和装置。 在特定实施例中，公开了一种方法，其包括将从主机设备接收的时间标记与从非易失性存储器的第一区域的数据存储设备检索的第一时间标记进行比较，所述第一区域包括最近访问的 数据存储设备内的存储器阵列的区域。 该方法还包括基于从主机设备接收的时间戳和与阈值相比较的第一时间戳之间的差异的比较来选择性地刷新第一区域，其中基于对应于第一时间戳的第一错误计数来调整阈值 由纠错码（ECC）引擎相对于从第一区域检索的数据检测到的错误的数量。

公开(公告)号：US20100332923A1

公开(公告)日：2010-12-30

申请号：US12494222

申请日：2009-06-29

申请人： MANUEL ANTONIO D'ABREU ,  STEPHEN SKALA ,  DANA LEE

发明人： MANUEL ANTONIO D'ABREU ,  STEPHEN SKALA ,  DANA LEE

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F12/02

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/4402

摘要： Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.

摘要翻译： 公开了响应于存储器的性能参数的变化率的系统和方法。 在特定实施例中，确定非易失性存储器的性能参数的变化率。 将变化率与阈值进行比较，并且响应于确定变化率满足阈值来执行动作。