公开(公告)号：US07889554B2

公开(公告)日：2011-02-15

申请号：US12624258

申请日：2009-11-23

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。

公开(公告)号：US20100020616A1

公开(公告)日：2010-01-28

申请号：US12572098

申请日：2009-10-01

申请人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

发明人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC分类号： G11C16/04

CPC分类号： G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

摘要翻译： 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

公开(公告)号：US07548461B2

公开(公告)日：2009-06-16

申请号：US10874825

申请日：2004-06-22

申请人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

发明人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC分类号： G11C11/34

CPC分类号： G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

公开(公告)号：US20080192546A1

公开(公告)日：2008-08-14

申请号：US12061020

申请日：2008-04-02

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US06996008B2

公开(公告)日：2006-02-07

申请号：US10841406

申请日：2004-05-06

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

公开(公告)号：US5471478A

公开(公告)日：1995-11-28

申请号：US401942

申请日：1995-03-10

申请人： John S. Mangan ,  Robert D. Norman ,  Jeffrey Craig ,  Richard Albert ,  Anil Gupta ,  Jeffrey D. Stai ,  Karl M. J. Lofgren

发明人： John S. Mangan ,  Robert D. Norman ,  Jeffrey Craig ,  Richard Albert ,  Anil Gupta ,  Jeffrey D. Stai ,  Karl M. J. Lofgren

IPC分类号： G06F3/06 ,  G06F11/10 ,  G11C16/10 ,  G11C29/00 ,  G06F11/00

CPC分类号： G11C29/765 ,  G06F3/0601 ,  G11C16/102 ,  G06F11/1068 ,  G06F2003/0694

摘要： A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

摘要翻译： 在闪存电可擦除和可编程只读存储器（“EEPROM”）系统中采用的文件结构以及在这样的文件结构内形成和使用某些数据字段的方面。 EEPROM存储器单元的行和列的阵列被划分为可单独寻址以便同时擦除整个单元块的单元的单元块。 每个块包含几行单元，其中某些列存储数据扇区（通常为512字节的数据），同一行内的其他单元格列用作备用单元以替代任何缺陷扇区数据单元并存储开销（标题） 关于块和数据扇区的信息。 这种开销信息包括指向块内的任何缺陷扇区数据单元的位置的指针，该块是否被映射到有利于另一个块，扇区数据的纠错码和头部信息以及其他类似类型的信息。

公开(公告)号：US08503240B2

公开(公告)日：2013-08-06

申请号：US13550157

申请日：2012-07-16

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US20110134696A1

公开(公告)日：2011-06-09

申请号：US13027055

申请日：2011-02-14

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US20100067298A1

公开(公告)日：2010-03-18

申请号：US12624258

申请日：2009-11-23

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US20100049910A1

公开(公告)日：2010-02-25

申请号：US12611280

申请日：2009-11-03

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.