公开(公告)号：US07176818B2

公开(公告)日：2007-02-13

申请号：US11176153

申请日：2005-07-06

Applicant: Filippo Marino ,  Eliana Cannella

Inventor： Filippo Marino ,  Eliana Cannella

IPC: H03M3/00

CPC classification number: H03M1/208

Abstract: An apparatus adapted to convert an input analog signal to an output digital signal includes means adapted to convert a first digital value of the output signal of the apparatus to a first analog value (IN1), wherein the first digital value is emitted by the apparatus at a first time instant, and also means for feeding back the first analog value to the input of the apparatus. The apparatus includes first means adapted to determine the difference between the first analog value and a second analog value (IN) of the input signal at a second time instant successive to the first time instant. The apparatus also includes second means adapted to convert the difference to a digital value and third means adapted to add or subtract the digital value of the difference to or from said first digital value by obtaining the output digital signal.

Abstract translation: 适于将输入模拟信号转换为输出数字信号的装置包括适于将装置的输出信号的第一数字值转换为第一模拟值（IN 1）的装置，其中第一数字值由装置发射 并且还用于将第一模拟值反馈给设备的输入的装置。 该装置包括适于在连续到第一时刻的第二时刻确定输入信号的第一模拟值和第二模拟值（IN）之间的差的第一装置。 该装置还包括适于将差值转换为数字值的第二装置，以及适于通过获得输出数字信号将差值的数字值与所述第一数字值相加或相减的第三装置。

公开(公告)号：US20060007032A1

公开(公告)日：2006-01-12

申请号：US11176153

申请日：2005-07-06

Applicant: Filippo Marino ,  Eliana Cannella

Inventor： Filippo Marino ,  Eliana Cannella

IPC: H03M1/12

CPC classification number: H03M1/208

Abstract: An apparatus adapted to convert an input analog signal to an output digital signal includes means adapted to convert a first digital value of the output signal of the apparatus to a first analog value (IN1), wherein the first digital value is emitted by the apparatus at a first time instant, and also means for feeding back the first analog value to the input of the apparatus. The apparatus includes first means adapted to determine the difference between the first analog value and a second analog value (IN) of the input signal at a second time instant successive to the first time instant. The apparatus also includes second means adapted to convert the difference to a digital value and third means adapted to add or subtract the digital value of the difference to or from said first digital value by obtaining the output digital signal.

Abstract translation: 适于将输入模拟信号转换为输出数字信号的装置包括适于将装置的输出信号的第一数字值转换为第一模拟值（IN 1）的装置，其中第一数字值由装置发射 并且还用于将第一模拟值反馈给设备的输入的装置。 该装置包括适于在连续到第一时刻的第二时刻确定输入信号的第一模拟值和第二模拟值（IN）之间的差的第一装置。 该装置还包括适于将差值转换为数字值的第二装置，以及适于通过获得输出数字信号将差值的数字值与所述第一数字值相加或相减的第三装置。

公开(公告)号：US06894627B2

公开(公告)日：2005-05-17

申请号：US10663729

申请日：2003-09-17

Applicant: Seetharaman Janakiraman ,  Kiran Manohar Godbole ,  Surendranath Nagesh

Inventor： Seetharaman Janakiraman ,  Kiran Manohar Godbole ,  Surendranath Nagesh

IPC: H03M1/06 ,  H03M1/20 ,  H03M7/20

CPC classification number: H03M1/06 ,  H03M1/0656 ,  H03M1/208

Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.

Abstract translation: 通过从相同的模拟采样产生多个N位代码并对N位代码进行平均，将模拟信号转换为N位数字码，具有高SNR（信噪比）。 然而，整个N位代码仅被确定一次，并且仅产生P位（P小于N）个代码。 可以对P位代码进行平均，并且基于平均值校正N位代码以产生精确的N位数字代码。 由于P可以远小于N，所以可以在几次迭代中实现校正，从而使得能够以高吞吐量性能实现ADC。 由于校正，也可以获得高SNR。

公开(公告)号：US06414619B1

公开(公告)日：2002-07-02

申请号：US09945926

申请日：2001-09-04

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03M112

CPC classification number: H03M1/185 ,  H03M1/187 ,  H03M1/208

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

Abstract translation: 提供了一种自动量程模数转换系统。 该系统可以包括用于放大模拟输入和模拟输入的估计之间的差的数字可编程前置放大器。 前置放大器可以耦合到模数转换器，用于将前置放大器输出转换成数字信号。 该系统还可以包括用于确定给定模拟输入的最佳增益和模拟输入估计的数字域预测器或估计逻辑。 多个信号输入通道可以耦合到模数转换系统。 自动量程估计可以根据样本或逐个频道进行。

公开(公告)号：US06310518B1

公开(公告)日：2001-10-30

申请号：US09429002

申请日：1999-10-29

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03G320

CPC classification number: H03M1/765 ,  H03M1/185 ,  H03M1/187 ,  H03M1/208

Abstract: A programmable gain preamplifier is provided which has a low temperature drift and good dynamic range characteristics. The programmable gain preamplifier provides a programmable gain of the difference between two input signals (Ain and Ain′ for example). One of the input signals (Ain′) may be an estimation of the other input signal (Ain). The estimation input signal (or a signal related to the estimated input) may be generated by the use of a reference voltage and a first resistor string. More particularly, the reference voltage and the first resistor string may operate as a digital to analog converter (DAC) that converts a digital estimation signal to an analog estimation voltage. The analog estimation voltage operates as an analog voltage that is a function of (or the same as) the analog Ain′ estimation signal. The first resistor string may provide the estimation voltage without loading the resistor string. Thus, the first resistor string may be simultaneously utilized by other circuitry, such as for example, a downstream ADC. The programmable preamplifier gain may be set by the use of a second resistor string and digitally programmable switches. Contacts to the resistors strings may be placed outside of the current path of each resistor string to provide highly stable resistor strings having a very low temperature drift. In one preamplifier embodiment, some or all of the opamps may chopper stabilized opamps, at least one opamp may be a current feedback opamp, the resistor strings may be at least 64 resistors long and programmable gains from 1 to 32 may be provided.

Abstract translation: 提供了一种可编程增益前置放大器，具有低温度漂移和良好的动态范围特性。 可编程增益前置放大器提供两个输入信号（例如Ain和Ain'）之间差异的可编程增益。 输入信号（Ain'）中的一个可以是另一个输入信号（Ain）的估计。 可以通过使用参考电压和第一电阻串来产生估计输入信号（或与估计输入相关的信号）。 更具体地，参考电压和第一电阻器串可以作为将数字估计信号转换为模拟估计电压的数模转换器（DAC）来操作。 模拟估计电压作为模拟电压作为模拟电压估计信号的（或相同）的函数。 第一电阻器串可以提供估计电压而不加载电阻器串。 因此，第一电阻器串可以被其他电路同时使用，例如下游ADC。 可编程前置放大器增益可以通过使用第二电阻器串和数字可编程开关来设定。 与电阻器串的接触可以放置在每个电阻器串的电流路径之外，以提供具有非常低的温度漂移的高度稳定的电阻器串。 在一个前置放大器实施例中，一些或所有运算放大器可以斩波稳定的运算放大器，至少一个运算放大器可以是电流反馈运算放大器，电阻器串可以是至少64个电阻器长，并且可以提供从1到32的可编程增益。

公开(公告)号：US06288664B1

公开(公告)日：2001-09-11

申请号：US09442026

申请日：1999-11-17

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03M118

CPC classification number: H03M1/208 ,  H03M1/185 ,  H03M1/187

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

Abstract translation: 提供了一种自动量程模数转换系统。 该系统可以包括用于放大模拟输入和模拟输入的估计之间的差的数字可编程前置放大器。 前置放大器可以耦合到模数转换器，用于将前置放大器输出转换成数字信号。 该系统还可以包括用于确定给定模拟输入的最佳增益和模拟输入估计的数字域预测器或估计逻辑。 多个信号输入通道可以耦合到模数转换系统。 自动量程估计可以根据样本或逐个频道进行。

公开(公告)号：US6100834A

公开(公告)日：2000-08-08

申请号：US79965

申请日：1998-05-15

Applicant: Lanny L. Lewyn

Inventor： Lanny L. Lewyn

IPC: H03M3/04 ,  H03M1/20 ,  H03M1/10

CPC classification number: H03M1/208

Abstract: A flash converter is preceded by an accurate continuous-time error amplifier operating on the difference between the input signal and a feedback DAC. The DAC output is operatively coupled to the amplifier input virtual ground or summing node through, for example, a set of precision capacitors. The input circuit is also coupled to the amplifier input through a continuous-time element such as a set of precision capacitors, approximately equal in capacitance to those coupled to the DAC. The amplifier may have a moderate closed-loop forward gain such as 16 with a high-pass characteristic beyond, for example, 10 Hz. The DAC is controlled by the latched output of a digital signal processing block, which uses digital outputs from the flash converter and the last latched output to predict the next value of the input signal. Converter control loop stability is afforded by providing a lowpass character to the prediction circuit. The converter produces a digital result by adding the digital value produced by the flash, properly scaled, to the current digital output value of the digital latch driving the DAC. The digital result may be sub-sampled at any arbitrary phase of the input sampling clock to permit optimum-phase data recovery.

Abstract translation: 闪存转换器之前是一个准确的连续时间误差放大器，用于输入信号和反馈DAC之间的差异。 DAC输出通过例如一组精密电容器可操作地耦合到放大器输入虚拟接地或求和节点。 输入电路还通过诸如一组精密电容器的连续时间元件耦合到放大器输入，其电容几乎与耦合到DAC的电容相等。 放大器可以具有适度的闭环正向增益，例如16，具有超过例如10Hz的高通特性。 DAC由数字信号处理模块的锁存输出控制，数字信号处理模块使用闪存转换器的数字输出和最后锁存的输出来预测输入信号的下一个值。 通过向预测电路提供低通字符来提供转换器控制环路的稳定性。 转换器通过将闪存产生的数字值（适当缩放）与驱动DAC的数字锁存器的当前数字输出值相加来产生数字结果。 数字结果可以在输入采样时钟的任意任意阶段进行子采样，以允许最佳相位数据恢复。

公开(公告)号：US06002352A

公开(公告)日：1999-12-14

申请号：US881690

申请日：1997-06-24

Applicant: Hussein S. El-Ghoroury ,  Steven D. Hall ,  Matthew Millward

Inventor： Hussein S. El-Ghoroury ,  Steven D. Hall ,  Matthew Millward

IPC: H03M1/12 ,  H03D7/00 ,  H03M1/20 ,  H04B1/26 ,  H03M1/18

CPC classification number: H03M1/208

Abstract: A simple down converting A/D converter utilizing predictive coding principles. By placing the sampler inside the predictive loop, the predictive loop filter can be implemented using DSP techniques, thus eliminating the complexities introduced by use of discrete-time analog circuitry. Then, by re-mapping the output of the predictive loop filter into the analog domain using a D/A converter, the predictive filter output signal is subtracted from the input analog signal to generate the prediction error signal. Therefore, through directly sampling the prediction error signal and converting the output of the predictive loop filter into analog representation using a low-cost multiple bit D/A, the use of discrete-time analog circuitry is eliminated and the complexity of the converter design is greatly reduced. Various features of the invention are disclosed.

Abstract translation: 一种利用预测编码原理的简单的下变频A / D转换器。 通过将采样器放置在预测环路内，可以使用DSP技术实现预测环路滤波器，从而消除了使用离散时间模拟电路引入的复杂性。 然后，通过使用D / A转换器将预测环路滤波器的输出重新映射到模拟域，从输入的模拟信号中减去预测滤波器输出信号，以产生预测误差信号。 因此，通过直接采样预测误差信号并将预测环路滤波器的输出转换为模拟表示，使用低成本多位D / A，消除了离散时间模拟电路的使用，并且转换器设计的复杂性是 大大减少。 公开了本发明的各种特征。

公开(公告)号：US5317313A

公开(公告)日：1994-05-31

申请号：US074333

申请日：1993-06-09

Applicant: Jurgen Kasser

Inventor： Jurgen Kasser

IPC: H03M1/12 ,  H03M1/20 ,  H03M1/40

CPC classification number: H03M1/208

Abstract: In an A/D converter for electrical signals, the difference, between the instantaneous analog input signal Y(t) and a previous analog signal value Y(t-T), is converted in a fast analog-to-digital converter (3) to a digital sum value. This sum value is added to the preceding digital value, stored in a buffer memory (7, 7'), and the result is fed to a slow but precise D/A converter (2) for generation of the next Y(t-T) value. This has the advantage that good results can be obtained with A/D converters less expensive than those heretofore required to obtain such results.

Abstract translation: 在用于电信号的A / D转换器中，瞬时模拟输入信号Y（t）和先前的模拟信号值Y（tT）之间的差在快速模数转换器（3）中被转换成 数字和值。 将该和值加到先前的数字值中，存储在缓冲存储器（7,7'）中，并将结果馈送到慢但精确的D / A转换器（2），以产生下一个Y（tT）值 。 这具有以下优点：A / D转换器可以获得比迄今为止所需的结果更便宜的结果。

公开(公告)号：US5287108A

公开(公告)日：1994-02-15

申请号：US908231

申请日：1992-07-02

Applicant: Michael K. Mayes ,  Sing W. Chin

Inventor： Michael K. Mayes ,  Sing W. Chin

IPC: H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/46 ,  H03M1/42

CPC classification number: H03M1/145 ,  H03M1/208 ,  H03M1/365 ,  H03M1/46

Abstract: An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring reference voltages produced by the resistance ladder circuit, and cover a predefined range of voltages above and below the voltage associated with the ten-bit value generated during the first two conversion cycles. Then a voltage derived from the input voltage is compared with these generated voltages to generate a correction value that is combined with the ten-bit value generated during the initial conversion cycles to produce a 12-bit conversion value.

Abstract translation: 模数转换器（ADC）具有至少一个电阻梯形电路，用于产生阶梯式系列参考电压和一组比较器电路，用于将输入电压或由其导出的电压与步进电机的至少一个子集进行比较 一系列参考电压。 来自电阻梯形电路的参考电压以4 LSB为增量步进，其中1 LSB是对应于ADC输出值的一位变化的电压差。 在初始转换周期期间，产生表示输入电压的十位数字转换值。 在最后一个转换周期中，使用“并联逐次逼近寄存器”电路将两个额外的分辨率位加到转换值。 最后一个转换周期还可以纠正数字转换值前十位中高达+ -6 LSB的错误。 通过用二进制加权电容器选择性地切换参考电压的组合，在第三转换周期中产生一组连续的比较电压。 所得到的比较电压以1 LSB的增量进行分级，这是电阻梯形电路产生的相邻参考电压之间的电压增量的四分之一，并覆盖高于和低于与在 前两个转换周期。 然后将来自输入电压的电压与这些产生的电压进行比较，以产生与在初始转换周期期间产生的十位值相组合以产生12位转换值的校正值。