公开(公告)号：US20100171630A1

公开(公告)日：2010-07-08

申请号：US12349643

申请日：2009-01-07

申请人： Michael Alexander Carralero ,  Kirby J. Keller ,  Charles E. Morris

发明人： Michael Alexander Carralero ,  Kirby J. Keller ,  Charles E. Morris

IPC分类号： G08B7/00

CPC分类号： G07C5/085 ,  B60R16/0232 ,  H04L1/242 ,  H04L2001/0094

摘要： A method, apparatus, and computer program product for processing health management data for a vehicle. A plurality of modulated signals is received on a bus system in the vehicle. The plurality of modulated signals contains health management data from a plurality of data acquisition units. Each modulated signal has a different frequency from another modulated signal in the plurality of modulated signals to form a plurality of frequencies. The plurality of frequencies is selected to avoid interference with other data transmitted over the bus system by a plurality of data processing systems in the vehicle. The plurality of modulated signals is processed based on the plurality of frequencies used to transmit the plurality of modulated signals.

摘要翻译： 一种用于处理车辆健康管理数据的方法，装置和计算机程序产品。 在车辆中的总线系统上接收多个调制信号。 多个调制信号包含来自多个数据采集单元的健康管理数据。 每个调制信号具有与多个调制信号中的另一调制信号不同的频率，以形成多个频率。 选择多个频率以避免与车辆中的多个数据处理系统在总线系统上传输的其他数据的干扰。 基于用于发送多个调制信号的多个频率来处理多个调制信号。

公开(公告)号：US20100131686A1

公开(公告)日：2010-05-27

申请号：US12593678

申请日：2008-03-22

申请人： Andre Korrek

发明人： Andre Korrek

IPC分类号： G06F13/42

CPC分类号： H04L1/0041 ,  G05B19/0428 ,  H03M13/09 ,  H04L1/0061 ,  H04L1/007 ,  H04L12/417 ,  H04L2001/0094

摘要： The invention relates to a method and system for secure transmission of process data to be transmitted cyclically in a cyclical data transmission to be performed protocol-specifically via a transmission channel between a user functioning as a master and at least one user functioning as a slave that are connected to the transmission channel. Within a transmission protocol frame, a time slot that can always accommodate the same number of bits independently of the data to be transmitted is assigned to each slave during a data transmission cycle. For safety-relevant process data that is to be transmitted during a data transmission cycle from a slave to at least one additional user, or that is to be transmitted during a data transmission cycle from a user to at least one slave, additional first protection data for recognizing error-free transmission of this safety-relevant process data is generated and transmitted in each case.

摘要翻译： 本发明涉及一种用于在循环数据传输中循环传输的过程数据的安全传输的方法和系统，以便特定地通过用作主设备的用户和作为从设备的至少一个用户之间的传输信道进行协议 连接到传输信道。 在传输协议帧内，在数据传输周期期间，可以将始终适应相同数量的位的时隙独立于待传输的数据分配给每个从机。 对于要在从从设备到至少一个附加用户的数据传输周期期间要发送或将在从用户到至少一个从站的数据传输周期期间传送的安全相关过程数据，附加的第一保护数据 为了识别该安全相关过程的无差错传输，在每种情况下产生和发送数据。

公开(公告)号：US20100118656A1

公开(公告)日：2010-05-13

申请号：US12267581

申请日：2008-11-08

申请人： Guillaume J. D. Tamboise ,  Christin Rendalen ,  Tristan Hollande

发明人： Guillaume J. D. Tamboise ,  Christin Rendalen ,  Tristan Hollande

IPC分类号： G01V1/22

CPC分类号： G01V1/22 ,  G01V1/04 ,  G01V1/06 ,  G01V1/26 ,  H04L1/0002 ,  H04L1/1607 ,  H04L1/1867 ,  H04L2001/0093 ,  H04L2001/0094 ,  H04L2001/0097

摘要： A method for use in a land-based seismic survey includes: transmitting a plurality of source control commands to a plurality of seismic sources over a VHF/IP network; and managing congestion on the VHF/IP network while transmitting the source control commands. In other aspects, a program storage medium encoded with instructions that, when executed by a processor, perform such a method and a computer programmed to perform such a method.

摘要翻译： 用于陆基地震勘测的方法包括：通过VHF / IP网络将多个源控制命令发射到多个地震源; 并在发送源控制命令的同时管理VHF / IP网络上的拥塞。 在其他方面，一种程序存储介质，其编码有当由处理器执行时执行这样的方法的指令和被编程为执行这种方法的计算机。

公开(公告)号：US20100014437A1

公开(公告)日：2010-01-21

申请号：US12407186

申请日：2009-03-19

申请人： Chuan-Hung Wang ,  Chien-Kuang Lin ,  Chin-Tai Liu ,  Chu-Ming Lin

发明人： Chuan-Hung Wang ,  Chien-Kuang Lin ,  Chin-Tai Liu ,  Chu-Ming Lin

IPC分类号： H04L12/56 ,  H04L12/26

CPC分类号： H04L47/10 ,  G06F11/0745 ,  G06F11/0793 ,  G06F11/1004 ,  H04L1/0052 ,  H04L1/0061 ,  H04L1/188 ,  H04L49/90 ,  H04L2001/0094

摘要： A method for data transmission in a device coupled to a host via a bus is provided. A sequence of data packets are received from the host and the received data packets are stored into a buffering unit of the device. It is then determined whether a predetermined error has occurred. When the predetermined error has occurred, the buffering unit of the device is locked to stop receiving the data packets. Thereafter, the buffering unit of the device is unlocked according to an unlock request from the host to resume receiving subsequent data packets.

摘要翻译： 提供了一种通过总线耦合到主机的设备中的数据传输方法。 从主机接收到数据分组序列，并将接收的数据分组存储到设备的缓冲单元中。 然后确定是否发生了预定的错误。 当发生预定错误时，设备的缓冲单元被锁定以停止接收数据分组。 此后，设备的缓冲单元根据来自主机的解锁请求解锁，以恢复接收后续数据分组。

公开(公告)号：US20090268736A1

公开(公告)日：2009-10-29

申请号：US12108637

申请日：2008-04-24

申请人： Brian D. Allison ,  Wayne M. Barrett ,  Mark L. Rudquist ,  Kenneth M. Valk ,  Brian T. Vanderpool

发明人： Brian D. Allison ,  Wayne M. Barrett ,  Mark L. Rudquist ,  Kenneth M. Valk ,  Brian T. Vanderpool

IPC分类号： H04L12/56

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L2001/0094

摘要： A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

摘要翻译： 提供了一种处理由总线发出的命令的方法。 该方法包括以下步骤：（1）将命令发送到远程节点以获得对完成命令所需的数据的访问; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）基于报头CRC验证响应分组; 和（4）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。

公开(公告)号：US07546512B2

公开(公告)日：2009-06-09

申请号：US10948896

申请日：2004-09-23

申请人： Prashant Ranjan ,  Jain Philip ,  Muralidharan S. Chilukoor

发明人： Prashant Ranjan ,  Jain Philip ,  Muralidharan S. Chilukoor

IPC分类号： H03M13/00

CPC分类号： H04L1/0041 ,  H04L1/0057 ,  H04L1/0061 ,  H04L2001/0094

摘要： Method and apparatus to perform cyclic redundancy check computations for error detection are described wherein a first stage includes a first set of computation elements, a first multiplexer and a second multiplexer. A latch is connected to the first stage. A second stage is connected to the latch and the second stage includes a second set of computation elements and a third multiplexer. The first stage and the second stage perform cyclic redundancy check computations for a packet, with the first set of computation elements performing cyclic redundancy check computations for a first set of bytes of input data from the packet, and the second set of computation elements performing cyclic redundancy check computations for a second set of bytes of input data from the packet. Other embodiments are described and claimed.

摘要翻译： 描述了执行用于错误检测的循环冗余校验计算的方法和装置，其中第一级包括第一组计算元件，第一多路复用器和第二多路复用器。 闩锁连接到第一级。 第二级连接到锁存器，第二级包括第二组计算元件和第三复用器。 第一级和第二级对分组执行循环冗余校验计算，其中第一组计算元素针对来自分组的输入数据的第一组字节执行循环冗余校验计算，并且第二组计算元素执行循环 对来自分组的输入数据的第二组字节的冗余校验计算。 描述和要求保护其他实施例。

公开(公告)号：US20090125789A1

公开(公告)日：2009-05-14

申请号：US12140643

申请日：2008-06-17

申请人： Richard Ferrant ,  Cedric Maufront

发明人： Richard Ferrant ,  Cedric Maufront

IPC分类号： G06F11/10

CPC分类号： H04L25/14 ,  H04L1/0043 ,  H04L2001/0094

摘要： A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

摘要翻译： 包括串联耦合的多个逻辑块的数据总线，每个逻辑块包括用于缓冲经由数据总线传输的至少一个数据位的至少一个缓冲器，以及至少一个逻辑块，还包括与该数据总线并联耦合的电路 至少一个缓冲器，并被布置成确定与所述至少一个数据位相关联的纠错码的第一位。

公开(公告)号：US20090100201A1

公开(公告)日：2009-04-16

申请号：US12341438

申请日：2008-12-22

申请人： Andrew B. Moch ,  Aaron T. Rossetto ,  Brent C. Schwan ,  Glen O. Sescila, III

发明人： Andrew B. Moch ,  Aaron T. Rossetto ,  Brent C. Schwan ,  Glen O. Sescila, III

IPC分类号： G06F3/00

CPC分类号： H04L1/24 ,  H04L43/50 ,  H04L2001/0094

摘要： A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

摘要翻译： 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。

公开(公告)号：US07502992B2

公开(公告)日：2009-03-10

申请号：US11394919

申请日：2006-03-31

申请人： Phillip Leef ,  Douglas Sullivan ,  Stephen Strickland ,  Alex Sanville

发明人： Phillip Leef ,  Douglas Sullivan ,  Stephen Strickland ,  Alex Sanville

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： H04L1/0061 ,  H04L1/16 ,  H04L2001/0094

摘要： A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.

摘要翻译： 数据存储系统包括存储处理器，其被配置为代表外部设备对存储阵列执行加载和存储操作。 数据存储系统还包括控制器，其通过存储处理器耦合到存储阵列时隔离外部设备之间的通信。 控制器还保持一组寄存器，其存储与数据存储系统相关联的信息，并允许存储处理器经由I2C总线访问寄存器。 系统利用错误检测程序来检测在控制器和存储处理器之间传输的数据中的错误。 在运行期间，在寄存器写入或读取过程期间，使用I2C总线在控制器和存储处理器之间传输校验和值。 控制器和存储处理器利用错误检测过程中的校验和值来检测由I2C总线传输数据的数据错误。

公开(公告)号：US20080149715A1

公开(公告)日：2008-06-26

申请号：US12043005

申请日：2008-03-05

申请人： Akihisa Fujimoto

发明人： Akihisa Fujimoto

IPC分类号： G06K7/00

CPC分类号： G06F3/0679 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0659 ,  G06F2003/0697 ,  G06F2206/1014 ,  G11C5/143 ,  H04L1/0061 ,  H04L2001/0094

摘要： A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

摘要翻译： 主机设备被配置为从卡读取和写入信息并提供属于低于第一电压范围的第一电压范围或第二电压范围的电源电压，并且向 卡。 电压识别命令包括电压范围识别部分，错误检测部分和检查模式部分。 电压范围识别部分包括指示电源电压所属的第一电压范围和第二电压范围中的哪一个的信息。 错误检测部具有被配置为使已经接收到电压识别命令的卡能够检测电压识别命令中的错误的模式。 检查图案部分具有预设图案。