公开(公告)号：US06542949B1

公开(公告)日：2003-04-01

申请号：US09436206

申请日：1999-11-08

申请人： Robert Earl Kruse

发明人： Robert Earl Kruse

IPC分类号： G06F1336

CPC分类号： G06F13/362 ,  G06F13/1605 ,  G06F13/1657

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. In addition, a bus arbiter in the node controller parks a data bus towards a memory subsystem. The node controller does not use data buffer reservations. The data bus grant line to the memory controller is overloaded to use it as a back-pressure, get-off-the-bus signal as well as a normal data bus grant line. The fairness of the bus is thereby increased by creating a mechanism for getting a “parked” device off the data bus without the use of another dedicated signal between physical components. To ensure that the node controller may stream data to the memory subsystem, the bus is not reparked towards the memory subsystem until a configurable number of cycles after the data bus has been granted to the node controller.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收事务，与主设备作为另一个主设备或从设备通信，并对从主设备接收的事务进行排队。 由于一致性的实现在时间和空间上分布，所以节点控制器有助于维持高速缓存一致性。 此外，节点控制器中的总线仲裁器将数据总线驻留到存储器子系统。 节点控制器不使用数据缓冲区保留。 到存储器控制器的数据总线授权线路过载，将其用作背压，断开总线信号以及普通数据总线授权线路。 因此，通过创建一种使“停放”设备离开数据总线而不在物理组件之间使用另一个专用信号的机制，从而增加总线的公平性。 为了确保节点控制器可以将数据流传输到存储器子系统，总线不向存储器子系统重放，直到数据总线已被授予节点控制器之后的可配置数量的周期。

公开(公告)号：US06487171B1

公开(公告)日：2002-11-26

申请号：US09315214

申请日：1999-05-19

申请人： Yoav Honig ,  Meir Ohana ,  Amir Lahat

发明人： Yoav Honig ,  Meir Ohana ,  Amir Lahat

IPC分类号： G06F1336

CPC分类号： H04L49/201 ,  H04L47/15 ,  H04L49/101 ,  H04L49/205 ,  H04L49/3027

摘要： A novel crossbar switching matrix that improves the transmission of variable length broadcast packets by greatly reducing transmission latency time. Unicast traffic is halted in the middle of packet transmission operations and the broadcast packet is transmitted. Once the broadcast packet has finished transmission, unicast packet transmission resumes without any loss of data. A unicast buffer is used to store the unicast packet while the broadcast packet is being transmitted. A broadcast buffer is used to buffer the broadcast packet as it egresses from the switch matrix. In this fashion, the broadcast information is given high priority and passes quickly through the switch without the large delays associated with the prior art switch matrixes. The crossbar switch matrix of the present invention is applicable to any switching matrix adapted to switch variable length data units.

摘要翻译： 一种新颖的交叉开关矩阵，通过大大减少传输延迟时间来改善可变长度广播数据包的传输。 单播流量在分组传输操作中停止，广播分组被发送。 一旦广播分组完成传输，单播分组传输将恢复，而不会丢失任何数据。 单播缓冲器用于在发送广播数据包时存储单播数据包。 当广播数据包从交换矩阵中出来时，广播缓冲区用于缓冲广播数据包。 以这种方式，广播信息被给予高优先级并且快速通过交换机而没有与现有技术的开关矩阵相关联的大的延迟。 本发明的交叉开关矩阵可应用于适于切换可变长度数据单元的任何开关矩阵。

公开(公告)号：US06463496B1

公开(公告)日：2002-10-08

申请号：US09339648

申请日：1999-06-24

申请人： Wolfgang Klein ,  Martin Burger ,  Philipp Eidner ,  Gunther Rentschler

发明人： Wolfgang Klein ,  Martin Burger ,  Philipp Eidner ,  Gunther Rentschler

IPC分类号： G06F1336

CPC分类号： G06F13/4291

摘要： The interface circuit serves for connecting two apparatus by way of a bidirectional bus which comprises a data lead for transmitting data and a cycle lead for transmitting a cycle signal. The interface circuit consists of a circuit arrangement provided at each apparatus, which comprises a separating means for separating the data signal on the data lead and the cylce signal on the cycle lead in each case into a transmitting and a receiving branch, and which furthermore comprises in each case for the data lead and the cylce lead a bus driver having a differential transmitter and receiver. The data signals and cylce signals between the apparatus are transmitted via differential leads.

摘要翻译： 接口电路用于通过双向总线连接两个装置，该双向总线包括用于发送数据的数据引线和用于发送周期信号的周期引线。 接口电路由在每个设备处提供的电路装置组成，包括用于将数据引线上的数据信号和循环引线上的信号信号分离成发送和接收分支的分离装置，还包括 在每种情况下，对于数据引线和cylce引线，具有差分发射器和接收器的总线驱动器。 设备之间的数据信号和信号信号通过差分引线传输。

公开(公告)号：US06457091B1

公开(公告)日：2002-09-24

申请号：US09311911

申请日：1999-05-14

申请人： Ronald E. Lange ,  David Ross Evoy

发明人： Ronald E. Lange ,  David Ross Evoy

IPC分类号： G06F1336

CPC分类号： G06F13/4004

摘要： A computer system includes a host processor, a first PCI bus, a second PCI bus and a PCI-to-PCI bridge. The first PCI bus is coupled with the host processor. The PCI-to-PCI bridge interconnects the first and second PCI buses. The PCI-to-PCI bridge includes a first portion and a second portion. The first portion includes a first configuration register and the second portion includes a second configuration register. A method is also taught.

摘要翻译： 计算机系统包括主处理器，第一PCI总线，第二PCI总线和PCI至PCI桥。 第一个PCI总线与主机处理器耦合。 PCI-PCI桥连接第一和第二PCI总线。 PCI至PCI桥包括第一部分和第二部分。 第一部分包括第一配置寄存器，第二部分包括第二配置寄存器。 还教了一种方法。

公开(公告)号：US06363447B1

公开(公告)日：2002-03-26

申请号：US09332279

申请日：1999-06-12

申请人： Douglas A. Larson

发明人： Douglas A. Larson

IPC分类号： G06F1336

CPC分类号： G06F13/364

摘要： One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus arbitration circuit. A number of grant lines emanate from the bus arbitration circuit. An encoder circuit encodes the grant lines into a smaller number of encoded grant lines. A selector circuit selects outputs from between the encoded grant lines and a first subset of grant lines. These outputs pass through output pins off of the semiconductor chip. During a first mode of operation, the first subset of grant lines is driven through the plurality of output pins. During a second mode of operation, the encoded grant lines are driven through the output pins. A variation on the above embodiment includes a number of bus request lines, which are divided into a first subset and a second subset. The first subset of request lines feeds through a number of input pins into the bus arbitration circuit. During the first mode of operation, the second subset of request lines feeds from off of the semiconductor chip through a number of I/O pins and bi-directional buffers into the bus arbitration circuit. During the second mode of operation, the second subset of grant lines feeds from the bus arbitration circuit, through the bi-directional buffers and I/O pins and off of the semiconductor chip.

摘要翻译： 本发明的一个实施例提供了一种选择性地编码总线授权线以减少I / O引脚要求的装置。 该装置包括具有总线仲裁电路的半导体芯片。 总线仲裁电路产生了许多授权行。 编码器电路将许可线编码为较少数量的编码授权线。 选择器电路选择编码的许可线与授权线的第一子集之间的输出。 这些输出通过半导体芯片的输出引脚。 在第一操作模式期间，授权线的第一子集被驱动通过多个输出引脚。 在第二操作模式期间，经编码的授权线被驱动通过输出引脚。 上述实施例的变型包括多个总线请求线，其被划分为第一子集和第二子集。 请求线的第一个子集通过多个输入引脚馈送到总线仲裁电路。 在第一操作模式期间，请求线路的第二子集从半导体芯片通过多个I / O引脚和双向缓冲器馈送到总线仲裁电路中。 在第二操作模式期间，授权线路的第二子集通过双向缓冲器和I / O引脚从半导体芯片馈送总线仲裁电路。

公开(公告)号：US06363446B1

公开(公告)日：2002-03-26

申请号：US09332278

申请日：1999-06-12

申请人： Douglas A. Larson

发明人： Douglas A. Larson

IPC分类号： G06F1336

CPC分类号： G06F13/364

摘要： One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating from a bus arbitration circuit and encoding the grant lines into a smaller number of encoded grant lines. The method selects outputs from between the encoded grant lines and a first subset of the grant lines. These outputs are driven off of a semiconductor chip through a number of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the output pins. During a second mode of operation, the encoded grant lines are selected to driven through the output pins. In a variation on the above embodiment, the method additionally receives a number of bus request lines. These request lines are divided into a first subset and a second subset. The first subset of request lines is received through a number of input pins from off of the semiconductor chip. During the first mode of operation, the second subset of request lines is received from off of the semiconductor chip through a number of I/O pins and bi-directional buffers into the bus arbitration circuit. This first mode of operation allows more request lines to be used in conjunction with the plurality of encoded grant lines. During the second mode of operation, the second subset of bus grant lines feeds from the bus arbitration circuit through the bi-directional buffers and I/O pins and off of the semiconductor chip. This second mode of operation allows more pins to be used for grant lines when grant lines are not encoded.

摘要翻译： 本发明的一个实施例提供了一种用于选择性地编码总线授权线以减少I / O引脚要求的方法。 该方法包括接收从总线仲裁电路发出的许多授权线，并将许可线编码为较少数量的编码授权线。 该方法从编码的许可线和授权线的第一子集之间选择输出。 这些输出通过多个输出引脚从半导体芯片驱动。 在第一操作模式期间，授权线的第一子集被选择为通过输出引脚驱动。 在第二操作模式期间，编码的授权线被选择为通过输出引脚驱动。 在上述实施例的变型中，该方法另外接收多条总线请求线。 这些请求线被分成第一子集和第二子集。 通过从半导体芯片的外部的多个输入引脚接收请求线的第一子集。 在第一操作模式期间，通过多个I / O引脚和双向缓冲器从第二半导体芯片接收请求线的第二子集到总线仲裁电路中。 该第一操作模式允许更多的请求行与多个编码的许可行结合使用。 在第二操作模式期间，总线授权线路的第二子集通过双向缓冲器和I / O引脚从半导体芯片馈送总线仲裁电路。 这种第二种操作模式允许在授权线不被编码时，更多的引脚用于授权线路。

公开(公告)号：US06360305B1

公开(公告)日：2002-03-19

申请号：US09205456

申请日：1998-12-04

申请人： Stephen T. Novak ,  John C. Peck, Jr.

发明人： Stephen T. Novak ,  John C. Peck, Jr.

IPC分类号： G06F1336

CPC分类号： G06F13/1631

摘要： A memory controller for a dynamic random access memory which pre-charges active banks in a particular chip select when an eight quadword access is made to another bank within that same chip select. When the memory controller detects an eight quadword access which is a page hit or page miss within the same chip select, the memory controller will look for any other active banks on that chip select. If there is another active bank other than the bank being accessed by the eight quadword access, the memory controller will attempt to transmit a pre-charge operation to that bank in the clock cycle immediately following the acceptance of the eight quadword access.

摘要翻译： 一种用于动态随机存取存储器的存储器控​​制器，当在同一芯片选择中对另一个存储体进行八个四字访问时，预先对特定芯片中的活动存储体进行预充电。 当存储器控制器检测到在相同芯片选择内的页面命中或页面错失的八个四字访问时，存储器控制器将寻找该芯片选择上的任何其他活动存储体。 如果存在除八个四字访问存取的银行以外的另一个活动存储区，则存储器控制器将尝试在接受八个四字访问之后的时钟周期中向该存储体发送预充电操作。

公开(公告)号：US06256697B1

公开(公告)日：2001-07-03

申请号：US09223638

申请日：1998-12-30

申请人： Jasmin Ajanovic ,  David J. Harriman

发明人： Jasmin Ajanovic ,  David J. Harriman

IPC分类号： G06F1336

CPC分类号： G06F13/36

摘要： An apparatus for reusing arbitration signals to frame data transfers between hub agents is disclosed. The apparatus includes an arbitration signal output circuit to output a first request signal to indicate a data transfer. The apparatus further includes a data path input/output unit to output data to a data path during a period indicated by the arbitration signal.

摘要翻译： 公开了一种用于重用仲裁信号以组合集线器代理之间的数据传输的装置。 该装置包括仲裁信号输出电路，用于输出第一请求信号以指示数据传送。 该装置还包括数据路径输入/输出单元，用于在由仲裁信号指示的时段期间向数据路径输出数据。

公开(公告)号：US06829669B2

公开(公告)日：2004-12-07

申请号：US09932377

申请日：2001-08-17

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa

IPC分类号： G06F1336

CPC分类号： G06F13/4059 ,  G06F13/4031

摘要： A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

摘要翻译： 一个总线桥被定义为提供两条AHB总线之间的接口。 这些总线通常具有单独的要求，但两者都必须提供高性能。 第一个是将数据从CPU传输到内存和外围设备。 第二个是支持通过单个外设向本地存储器或其他本地外围设备传输大量数据。 AHB到HTB总线桥提供了一种用于连接这两个单独的AHB总线的手段，从而允许它们之间的通信并保证数据的完整性。 本发明的总线桥被定义为AHB存储器总线从机，而是高性能数据传输总线主机。

公开(公告)号：US06813674B1

公开(公告)日：2004-11-02

申请号：US09570318

申请日：2000-05-12

申请人： Francisco Velasco ,  Xuyen N. Phung ,  Phillip M. Mitchell ,  Henry T. Fung

发明人： Francisco Velasco ,  Xuyen N. Phung ,  Phillip M. Mitchell ,  Henry T. Fung

IPC分类号： G06F1336

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3259 ,  G06F1/3271 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/155 ,  Y02D10/156

摘要： A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

摘要翻译： 具有主机FIFO接口的双边缘FIFO接口，其操作以在主机时钟的单个边缘上从主机模块接收数据，并且确定当读取数据FIFO中存在有效读取数据时或当读取数据FIFO满时 ，目标FIFO接口，用于从目标核心模块接收读取数据，传输数据，以及确定读取数据FIFO何时已满，以及与主机FIFO和目标FIFO通信的寄存器块，其中双边缘 FIFO接口可操作以在核心逻辑电平，块电平或芯片级别互连内部模块。