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    Computing system and method of verifying circuit design in computing system
    32.
    发明授权
    Computing system and method of verifying circuit design in computing system 有权

    公开(公告)号：US11907629B2

    公开(公告)日：2024-02-20

    申请号：US17552819

    申请日：2021-12-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soonwoo Choi ,  Jung Woon Lee ,  Junyoung Jeong

    IPC: G06F30/33 ,  G06F30/323 ,  G06F30/333

    CPC classification number: G06F30/33 ,  G06F30/323 ,  G06F30/333

    Abstract: A computing system configured to verify design of an integrated circuit (IC) includes a memory and a processor. The memory is configured to store computer executable instructions. The processor is configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language (HDL) code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the HDL code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.

    AUTOMATIC LOW LEVEL OPERATOR LOOP GENERATION, PARALLELIZATION AND VECTORIZATION FOR TENSOR COMPUTATIONS
    33.
    发明公开
    AUTOMATIC LOW LEVEL OPERATOR LOOP GENERATION, PARALLELIZATION AND VECTORIZATION FOR TENSOR COMPUTATIONS 审中-公开

    公开(公告)号：US20240028802A1

    公开(公告)日：2024-01-25

    申请号：US17964085

    申请日：2022-10-12

    Applicant: NEC Laboratories Europe GmbH

    Inventor： Nicolas Weber

    IPC: G06F30/323 ,  G06F30/327

    CPC classification number: G06F30/323 ,  G06F30/327

    Abstract: A method is provided for transforming a high-level language representation of a tensor computation graph into a low level language. The method includes assigning, for each input edge of each node in the tensor computation graph, a tensor shape, assigning, for each dimension of the input and output of each layer of the tensor computation graph, a loop primitive, and generating, from the tensor computation graph and the assigned loop primitives, an initial loop structure. The method further includes positioning the layers of the tensor computation graph within a nested loop structure to provide a final loop structure, collapsing loops in the final loop structure, and mapping the collapsed loops to hardware components configured to execute the collapsed loops.

    Wafer-scale large programmable device
    34.
    发明授权
    Wafer-scale large programmable device 有权

    公开(公告)号：US11803681B1

    公开(公告)日：2023-10-31

    申请号：US17209006

    申请日：2021-03-22

    Applicant: XILINX, INC.

    Inventor： Zachary Blair ,  Alireza Kaviani

    IPC: G06F30/323 ,  H01L25/065 ,  H01L27/02 ,  G06F30/3947

    CPC classification number: G06F30/323 ,  G06F30/3947 ,  H01L25/0655 ,  H01L27/0207

    Abstract: The embodiments herein rely on cross reticle wires (also referred to as cross die wires) to provide communication channels between programmable dies already formed on a wafer. Using cross reticle wires to facilitate x-die communication can be three to four orders of magnitude faster than using general purpose I/O. With a wafer containing cross reticle wires, various device geometries can be generated at dicing time by cutting across different reticle boundaries. This allows up to full wafer-size devices, or several smaller sub-wafer devices to be derived from one wafer. Although the programmable dies can contain defects, these defects can be identified and avoided when generating a bitstream for configuring programmable features in the programmable dies.

    Method of RF Analog Circuits Electronic Design Automation Based on GCN and Deep Reinforcement Learning
    37.
    发明公开
    Method of RF Analog Circuits Electronic Design Automation Based on GCN and Deep Reinforcement Learning 审中-公开

    公开(公告)号：US20230267250A1

    公开(公告)日：2023-08-24

    申请号：US17653880

    申请日：2022-03-08

    Applicant: Mitsubishi Electric Research Laboratories, Inc.

    Inventor： Rui Ma ,  Mouhacine Benosman ,  Weidong Cao

    IPC: G06F30/323 ,  G06N3/08 ,  G06N3/04

    CPC classification number: G06F30/323 ,  G06N3/08 ,  G06N3/0454

    Abstract: A computer-implemented method is provided for generating device parameters of circuits using a pretrained reinforcement learning (RL) agent composed of a graph neural network (GNN) and a fully connected neural network (FCNN). The method is performed by steps including acquiring inputs with respect to a set of desired specifications or one desired specification of a circuit, device parameters, a fixed topology of the circuit and providing the inputs to the RL agent. The desired circuit description includes a graph modeling the topology of the circuit and device parameters of the circuit, and the desired specifications include gain, bandwidth, phase margin, power consumption, output power and power efficiency. The pretrained RL agent performs steps including transmitting an action selected from a set of actions to an environment module, updating the device parameters of the circuit according to the selected action using a data processor of the environment module, obtaining a current specification of the circuit by simulating a netlist of the circuit, acquiring a reward from the environment module, and generating the updated device parameters of the circuit.

    Automatic sequential retry on compilation failure
    38.
    发明授权
    Automatic sequential retry on compilation failure 有权

    公开(公告)号：US11709984B2

    公开(公告)日：2023-07-25

    申请号：US17541886

    申请日：2021-12-03

    Applicant: Synopsys, Inc.

    Inventor： Guillaume Jean Baptiste Desplechain

    IPC: G06F30/3323 ,  G06F30/327 ,  G06F30/323 ,  G06F119/02

    CPC classification number: G06F30/3323 ,  G06F30/323 ,  G06F30/327 ,  G06F2119/02

    Abstract: A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT). The compilation system can determine a sequence of the compilation operations for the compiler to perform the compilation. The compilation system can detect a failure at a first compilation operation of the sequence of operations during the compilation of the DUT, and the compilation of the DUT can be paused after the failure is detected. The compilation system can determine a second compilation operation of the accessed compilation operations based on one or more netlist parameters of the DUT's netlist. The compilation system then modifies the sequence of compilation operations based on the second compilation operation and resumes the compilation of the DUT at the second compilation operation using the modified sequence of compilation operations.

    Techniques For Replacing Logic Circuits In Modules With Configurable Circuits
    39.
    发明公开
    Techniques For Replacing Logic Circuits In Modules With Configurable Circuits 审中-公开

    公开(公告)号：US20230222274A1

    公开(公告)日：2023-07-13

    申请号：US18124259

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： David Kehlet ,  Nij Dorairaj

    IPC: G06F30/323

    CPC classification number: G06F30/323

    Abstract: A computer system is provided for protecting a circuit design for an application specific integrated circuit. The computer system includes a logic circuit replacement tool for identifying a module of logic circuitry for replacement in at least a portion of the circuit design. The logic circuit replacement tool generates a transformed circuit design for the application specific integrated circuit by replacing the logic circuitry in the module with a configurable circuit that performs a logic function of the logic circuitry when a bitstream stored in storage circuits in the configurable circuit configures the configurable circuit. The transformed circuit design includes the configurable circuit in the module.

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