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37 条记录 (耗时 0.012 秒)

    Analog computer architecture for fast function optimization
    34.
    发明授权
    Analog computer architecture for fast function optimization 有权

    公开(公告)号：US11043951B2

    公开(公告)日：2021-06-22

    申请号：US16206206

    申请日：2018-11-30

    申请人： Palo Alto Research Center Incorporated

    发明人： Ion Matei ,  Aleksandar Feldman ,  Johan de Kleer

    IPC分类号： H03K19/17748 ,  G06G7/122 ,  G06G7/32

    摘要： An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.

    ANALOG COMPUTER ARCHITECTURE FOR FAST FUNCTION OPTIMIZATION
    35.
    发明申请
    ANALOG COMPUTER ARCHITECTURE FOR FAST FUNCTION OPTIMIZATION 有权

    公开(公告)号：US20210184680A1

    公开(公告)日：2021-06-17

    申请号：US17171824

    申请日：2021-02-09

    申请人： Palo Alto Research Center Incorporated

    发明人： Ion Matei ,  Aleksandar Feldman ,  Johan de Kleer

    IPC分类号： H03K19/17748 ,  G06G7/122 ,  G06G7/32

    摘要： An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.

    Data flow graph optimization techniques for RTL loops with conditional-exit statements
    36.
    发明授权
    Data flow graph optimization techniques for RTL loops with conditional-exit statements 有权

    公开(公告)号：US10943042B1

    公开(公告)日：2021-03-09

    申请号：US16733568

    申请日：2020-01-03

    申请人： Xilinx, Inc.

    发明人： Sumanta Datta ,  Aman Gayasen

    IPC分类号： G06F30/337 ,  H03K19/17748 ,  G06F119/12

    摘要： A computer-implemented method includes compiling a Register Transfer Level (RTL) code to form a data flow graph (DFG). The computer-implemented method includes identifying a chain of multiplexers in the DFG, wherein the chain of multiplexers includes exit multiplexers associated with a loop exit path and non-exit multiplexers. The computer-implemented method also includes traversing a topological order of the DFG in reverse. The computer-implemented method also includes computing fanin-cones for each two consecutive exit multiplexers. The computer-implemented method includes generating a truth table responsive to valid fanin-cones and back propagating select conditions for the each two consecutive exit multiplexers. The computer-implemented method includes eliminating an exit multiplexer from the each two consecutive exit multiplexers based on the truth table. The computer-implemented method further includes transforming the DFG to a new DFG based on the truth table.