公开(公告)号：US08630338B2

公开(公告)日：2014-01-14

申请号：US13206315

申请日：2011-08-09

Applicant: Marina Nicolas

Inventor： Marina Nicolas

IPC: H04N7/12 ,  H04B1/66 ,  H04N7/36

CPC classification number: H04N19/00703 ,  H04N5/145 ,  H04N7/014 ,  H04N19/51 ,  H04N19/521 ,  H04N19/56

Abstract: A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block.

Abstract translation: 提供了一种运动估计方法和装置，用于将先前的原始图像和下一个原始图像之间插入的图像处理成图像序列。 每个图像被分成与运动矢量相关联的像素块。 对于正在处理的图像的当前块，选择与被处理图像的块正在处理和/或关联的图像的块相关联的运动矢量。 从选定的运动矢量生成候选向量。 为每个候选向量计算一个错误。 基于候选运动矢量指向当前块的先前原始图像中的像素块的像素值和/或基于当前块的值，确定候选矢量子集的惩罚 下一原始图像中的像素块的像素，候选运动矢量指向的当前块。

公开(公告)号：US08610216B2

公开(公告)日：2013-12-17

申请号：US12859929

申请日：2010-08-20

Applicant: Philippe Galy ,  Christophe Entringer ,  Jean Jimenez

Inventor： Philippe Galy ,  Christophe Entringer ,  Jean Jimenez

IPC: H01L23/62

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/8611

Abstract: A structure for protecting an integrated circuit against electrostatic discharges, including a device for removing overvoltages between first and second power supply rails; and a protection cell connected to a pad of the circuit including a diode having an electrode, connected to a region of a first conductivity type, connected to the second power supply rail and having an electrode, connected to a region of a second conductivity type, connected to the pad and, in parallel with the diode, a thyristor having an electrode, connected to a region of the first conductivity type, connected to the pad and having a gate, connected to a region of the second conductivity type, connected to the first rail, the first and second conductivity types being such that, in normal operation, when the circuit is powered, the diode is non-conductive.

Abstract translation: 一种用于保护集成电路免受静电放电的结构，包括用于去除第一和第二电源轨之间的过电压的装置; 以及保护单元，其连接到所述电路的焊盘，所述保护单元包括二极管，所述二极管具有连接到所述第二导电类型的第一导电类型的区域并具有连接到第二导电类型的区域的电极的电极， 连接到焊盘，并且与二极管并联，具有连接到第一导电类型的区域的电极的晶闸管连接到焊盘并具有连接到第二导电类型的区域的栅极，连接到第二导电类型的区域 第一导轨，第一和第二导电类型使得在正常操作中，当电路通电时，二极管是非导通的。

公开(公告)号：US08582765B2

公开(公告)日：2013-11-12

申请号：US12182408

申请日：2008-07-30

Applicant: Pierre-Yvan Liardet ,  Yannick Teglia

Inventor： Pierre-Yvan Liardet ,  Yannick Teglia

IPC: H04L9/06 ,  H04K1/00

CPC classification number: H04L9/003 ,  H04L2209/046

Abstract: A method and a circuit for ciphering or deciphering data with a key by using at least one variable stored in a storage element and updated by the successive operations, the variable being masked by at least one first random mask applied before use of the key, then unmasked by at least one second mask applied after use of the key, at least one of the masks being dividable into several portions successively applied to the variable and which, when combined, represent the other mask.

Abstract translation: 一种用于通过使用存储在存储元件中并由连续操作更新的至少一个变量来用密钥加密或解密数据的方法和电路，所述变量被使用密钥之前应用的至少一个第一随机掩码掩蔽，然后 在使用该键之后施加的至少一个第二掩模未屏蔽，所述掩模中的至少一个可被分割成连续施加到所述变量的若干部分，并且当组合时表示另一掩码。

公开(公告)号：US08565030B2

公开(公告)日：2013-10-22

申请号：US13240861

申请日：2011-09-22

Applicant: Fady Abouzeid ,  Sylvain Clerc ,  Philippe Roche

Inventor： Fady Abouzeid ,  Sylvain Clerc ,  Philippe Roche

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C11/413

Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.

Abstract translation: 一种读取升压电路，被布置为在读取操作期间升高存储器件的一对互补位线之间的电压差，读取升压电路包括：第一晶体管，其适于由第一晶体管的第一位线 一对位线将一对位线的第二位线耦合到第一电源电压; 以及第二晶体管，其直接连接到地，并且适于由第二位线上的电压电平控制，以将第一位线耦合到地。

公开(公告)号：US08514123B2

公开(公告)日：2013-08-20

申请号：US13247001

申请日：2011-09-28

Applicant: Stéphane Le Tual ,  Mounir Boulemnakher ,  Pratap Narayan Singh

Inventor： Stéphane Le Tual ,  Mounir Boulemnakher ,  Pratap Narayan Singh

IPC: H03M1/34

CPC classification number: H03M1/468

Abstract: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

Abstract translation: 一种逐次逼近模数转换的方法，包括：在采样阶段期间，将输入信号耦合到多对电容器; 并且在转换阶段期间，将每对的第一电容器耦合到第一电源电压，将每对的第二电容器耦合到第二电源电压。

公开(公告)号：US20130201766A1

公开(公告)日：2013-08-08

申请号：US13754427

申请日：2013-01-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Anis Feki

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

Abstract translation: 易失性存储器包括执行数据写入和读取操作的易失性存储器单元。 存储单元以行和列排列并且分布在每列的第一分离的存储单元组中。 对于每列，存储器包括专用于写操作并连接到列的所有存储器单元的写位线，以及专用于读操作的读位线。 每个读位线连接到第一组存储器单元之一的所有存储单元。 列中的每个存储单元连接到单个读取位线。

公开(公告)号：US08486817B2

公开(公告)日：2013-07-16

申请号：US12794092

申请日：2010-06-04

Applicant: Perceval Coudrain ,  Philippe Coronel ,  Nicolas Buffet

Inventor： Perceval Coudrain ,  Philippe Coronel ,  Nicolas Buffet

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.

Abstract translation: 一种用于在其上形成部件的第一支撑件上形成三维结构的水平的方法，包括以下步骤：在第二半导体支架上形成具有插入的热氧化物层的单晶半导体衬底; 将单晶半导体衬底的自由表面放置在第一支撑件的上表面上; 消除了第二个半导体支持; 并将热氧化层减薄至能够形成栅极绝缘体的厚度。

公开(公告)号：US08405462B2

公开(公告)日：2013-03-26

申请号：US13006253

申请日：2011-01-13

Applicant: Baudouin Martineau ,  Olivier Richard

Inventor： Baudouin Martineau ,  Olivier Richard

IPC: H03F1/22

CPC classification number: H03F3/193

Abstract: A cascode amplifier comprising at least two phase-shift stages controllable between an input transistor having a control terminal connected to an input terminal of the amplifier, and an output terminal of the amplifier.

Abstract translation: 一种级联放大器，包括至少两个相移级，可在具有连接到放大器的输入端的控制端的输入晶体管与放大器的输出端之间控制。

公开(公告)号：US08386662B2

公开(公告)日：2013-02-26

申请号：US12817924

申请日：2010-06-17

Applicant: Andre Roger

Inventor： Andre Roger

IPC: G06F3/00 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F13/385

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract translation: 本发明涉及一种用于组织存储器中外围设备的寄存器的方法，所述外围设备包括要在存储器中寻址的至少一个控制寄存器以存储外围设备的配置数据，要在存储器中寻址的一个发送寄存器以存储数据 从存储器发送到外围设备，以及一个要在存储器中寻址的接收寄存器，用于存储要从外围设备发送到存储器的数据，该方法包括：在数据存储器范围内将发送/接收寄存器复制到不同的连续 地址 并且在与发送/接收寄存器已被复制的存储器范围相邻的存储器范围内的连续地址的存储器中实现控制寄存器。

公开(公告)号：US08359478B2

公开(公告)日：2013-01-22

申请号：US11968742

申请日：2008-01-03

Applicant: Loïc Bonizec ,  Stéphane Chesnais

Inventor： Loïc Bonizec ,  Stéphane Chesnais

IPC: G06F12/14

CPC classification number: G06F21/72 ,  G06F7/584 ,  G06F21/74 ,  H04L9/002 ,  H04L9/0662 ,  H04L2209/12

Abstract: A method and a system for protecting a static digital datum contained in a first element of an electronic circuit, intended to be exploited by a second element of this circuit, in which: on the side of the first element, the static datum is converted into a dynamic data flow by at least one first linear shift feedback register representing a different polynomial according to the value of the static datum; the dynamic flow is transmitted to the second element; and on the side of the second element, the received dynamic flow is decoded by at least one second shift register representing at least one of the polynomials that has been used by the first element.

Abstract translation: 一种用于保护旨在由该电路的第二元件利用的电子电路的第一元件中的静态数字数据的方法和系统，其中：在第一元件的一侧将静态数据转换为 由至少一个第一线性移位反馈寄存器根据静态数据的值表示不同的多项式的动态数据流; 动态流动被传送到第二元件; 并且在所述第二元件的一侧，所接收的动态流由至少一个第二移位寄存器解码，所述至少一个第二移位寄存器表示由所述第一元素使用的多项式中的至少一个。