公开(公告)号：US20080143936A1

公开(公告)日：2008-06-19

申请号：US12002385

申请日：2007-12-17

Applicant: Hua-Bin Wang

Inventor： Hua-Bin Wang

IPC: G02F1/1335 ,  G02B5/20

CPC classification number: G02F1/133514 ,  G02B5/201 ,  G02F2201/52

Abstract: An exemplary liquid crystal display (2) includes a liquid crystal panel (20), and a backlight module (22) located adjacent to the liquid crystal panel. The liquid crystal panel includes a first substrate assembly (24) and a second substrate assembly (26) parallel to the first substrate assembly. The second substrate assembly includes a color filter layer (262). The color filter layer includes red units, green units, and blue units. The red, green and blue units are approximately strip-shaped. A ratio of a width of each red unit to a width of each green unit is in direct proportion to a ratio of the wavelength of red light to the wavelength of green light. A ratio of the width of each green unit to a width of each blue unit is in inverse proportion to a ratio of the wavelength of green light to the wavelength of blue light.

Abstract translation: 示例性液晶显示器（2）包括液晶面板（20）和位于液晶面板附近的背光模块（22）。 液晶面板包括第一衬底组件（24）和平行于第一衬底组件的第二衬底组件（26）。 第二基板组件包括滤色器层（262）。 滤色器层包括红色单元，绿色单元和蓝色单元。 红色，绿色和蓝色单元大致为条形。 每个红色单元的宽度与每个绿色单元的宽度的比率与红色光的波长与绿色光的波长的比率成正比。 每个绿色单元的宽度与每个蓝色单元的宽度的比率与绿色光的波长与蓝色光的波长的比率成反比。

公开(公告)号：US20080139494A1

公开(公告)日：2008-06-12

申请号：US11751569

申请日：2007-05-21

Applicant: David B. Weiner ,  Bin Wang ,  Kenneth Ugen

Inventor： David B. Weiner ,  Bin Wang ,  Kenneth Ugen

IPC: A61K31/7052 ,  A61P37/02

CPC classification number: A61K31/7052 ,  A61K31/711 ,  A61K39/00 ,  A61K39/12 ,  A61K39/21 ,  A61K39/292 ,  A61K48/00 ,  A61K2039/53 ,  A61K2039/541 ,  C07K14/005 ,  C12N15/87 ,  C12N2730/10122 ,  C12N2730/10134 ,  C12N2740/13022 ,  C12N2740/13034 ,  C12N2740/16122 ,  C12N2740/16134 ,  C12N2740/16222 ,  C12N2740/16234 ,  C12N2740/16322 ,  C12N2770/24222

Abstract: Methods of inducing mucosal immunity in individuals against proteins and peptides are disclosed. The methods comprise the step of administering topically or by lavage into mucosal tissue selected from the group consisting of rectal, vaginal, urethral, sublingual and buccal, a nucleic acid molecule that comprises a nucleotide sequence that encodes a protein or peptide that comprises an epitope against which mucosal immunity is desired. The methods may be used to immunize and individual against a pathogen infection, hyperproliferative diseases or autoimmune diseases using nucleic acid molecules which encode proteins and peptides that share an epitope with a pathogen antigen or protein associated with cells involved in hyperproliferative diseases or autoimmune diseases, respectively,

Abstract translation: 公开了在个体中针对蛋白质和肽诱导粘膜免疫的方法。 所述方法包括向局部或通过灌洗施用选自直肠，阴道，尿道，舌下和颊部的粘膜组织的步骤，所述核酸分子包含编码蛋白质或肽的核苷酸序列，所述核苷酸序列包含针对 需要哪种粘膜免疫。 这些方法可以用于分别使用编码分别与参与过度增殖性疾病或自身免疫疾病的细胞相关的病原体抗原或蛋白质共享表位的蛋白质和肽的核酸分子对病原体感染，过度增殖性疾病或自身免疫疾病进行免疫和个体 ，

公开(公告)号：US20080055719A1

公开(公告)日：2008-03-06

申请号：US11469210

申请日：2006-08-31

Applicant: Raymond T. Perkins ,  Bin Wang ,  Eric Gardner ,  Douglas P. Hansen

Inventor： Raymond T. Perkins ,  Bin Wang ,  Eric Gardner ,  Douglas P. Hansen

IPC: G02B5/30 ,  G02B27/28

CPC classification number: G02B5/3058

Abstract: An inorganic, dielectric grid polarizer device includes a stack of film layers disposed over a substrate. Each film layer is formed of a material that is both inorganic and dielectric. Adjacent film layers each have different refractive indices. At least one of the film layers is discontinuous to form a form birefringent layer with an array of parallel ribs having a period less than 400 nm.

Abstract translation: 无机介电栅极偏振器装置包括设置在基板上方的一层薄膜层。 每个膜层由无机和电介质的材料形成。 相邻的膜层各自具有不同的折射率。 至少一个膜层是不连续的以形成具有周期小于400nm的平行肋阵列的形式双折射层。

公开(公告)号：US07315067B2

公开(公告)日：2008-01-01

申请号：US10884236

申请日：2004-07-02

Applicant: Bin Wang

Inventor： Bin Wang

IPC: H01L29/43

CPC classification number: H01L29/4983 ,  H01L29/4916 ,  H01L29/7835

Abstract: A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain terminal coupled to the second n+ doped region, a p+ doped region disposed in the substrate, a body terminal coupled to the p+ doped region, a dielectric layer disposed over the p− doped substrate and a portion of the n− well, a first trench disposed in the n− well, the trench filled with a dielectric material that is in contact with the dielectric layer, a second trench disposed at least partially in the n− well, the second trench filled with a dielectric material and isolating the second n+ region from the p+ region, and a gate partially or fully reversely doped with p+ implant (or an equivalent technique) and disposed over the dielectric layer and a portion of the first trench.

Abstract translation: 原生高压n沟道LDMOSFET包括p掺杂衬底，设置在p掺杂衬底中的第一n +掺杂区，耦合到第一n +掺杂区的源极，设置在衬底中的n阱， 设置在n阱中的第二n +掺杂区域，耦合到第二n +掺杂区域的漏极端子，设置在衬底中的p +掺杂区域，耦合到p +掺杂区域的主体端子，设置在p掺杂区域上的介电层 衬底和n阱的一部分，设置在n阱中的第一沟槽，填充有与介电层接触的电介质材料的沟槽，至少部分地设置在n阱中的第二沟槽， 填充有电介质材料并且将第二n +区域与p +区域隔离的第二沟槽，以及部分地或完全地反向掺杂p +注入（或等效技术）的栅极并设置在电介质层和第一沟槽的一部分上的栅极。

公开(公告)号：US20070296921A1

公开(公告)日：2007-12-27

申请号：US11475857

申请日：2006-06-26

Applicant: Bin Wang ,  Eric Gardner ,  Raymond Perkins

Inventor： Bin Wang ,  Eric Gardner ,  Raymond Perkins

IPC: G03B21/14

CPC classification number: G03B21/005 ,  G02B5/3058 ,  G02B27/1026 ,  G02B27/1033 ,  G02B27/1053 ,  G02B27/142 ,  G02B27/145 ,  G02B27/149 ,  G02B27/283 ,  G03B21/2073 ,  G03B33/12 ,  H04N9/3167

Abstract: A display apparatus includes a cube wire-grid polarizing beam splitter with a plate wire-grid polarizer disposed between a pair of prisms secured together to form a cube. A reflective spatial light modulator produces an image bearing color light beam. The cube wire-grid polarizing beam splitter is disposable in the image bearing color light beam to separate the image information and to produce a polarized image bearing color light beam. A pair of continuous film layers is disposed between the plate wire-grid polarizer and a forward prism with a forward layer adjacent the forward prism having a refractive index greater than both i) a refractive index of a rear layer adjacent the plate wire grid polarizer, and ii) a refractive index of the forward prism. A layer of ribs is disposed between the wires and a rear prism, and the ribs being aligned with and supporting the wires.

Abstract translation: 显示装置包括立方体线栅偏振分束器，其中板状线栅偏振器设置在固定在一起的一对棱镜之间以形成立方体。 反射空间光调制器产生图像承载彩色光束。 立体线栅偏振分束器在图像承载色光束中是一次性的，以分离图像信息并产生带有彩色光束的偏振图像。 一对连续膜层设置在板状线栅偏振器和前向棱镜之间，其中与正向棱镜相邻的正向层的折射率大于以下两者：i）邻近板状线栅极偏振器的后层的折射率， 和ii）前向棱镜的折射率。 一排肋设置在导线和后棱镜之间，并且肋与导线对准并支撑。

公开(公告)号：US07313451B2

公开(公告)日：2007-12-25

申请号：US10937905

申请日：2004-09-10

Applicant: Naoki Takayama ,  Bin Wang ,  Satoshi Harada

Inventor： Naoki Takayama ,  Bin Wang ,  Satoshi Harada

IPC: G06F17/00

CPC classification number: H01L21/67253

Abstract: With analysis data in the prior art, it is difficult to find out if a change regarded as a judgmental standard of the completion of seasoning has come from a change due to the seasoning, namely, change in condition of the interior of a processing container or come from another change based on a temperature change among respective dummy wafers and furthermore, it is difficult to judge whether the seasoning has been completed or not. Therefore, a plasma processing method of the present invention, which is a method for detecting the completion of seasoning in performing the seasoning by loading dummy wafers W into a processing container 2 of a plasma processing apparatus 1, includes a process of creating a predictive formula for predicting the completion of seasoning and another process of detecting the completion of seasoning in performing the seasoning, based on the predictive formula. The creation of the predictive formula is accomplished by performing a multivariate analysis against a plurality of measured data that can be obtained by first supplying dummy wafers W into the processing container 2, cooling down the interior of the processing container 2 and supplying a plurality of dummy wafers W into the processing container 2 again.

Abstract translation: 通过现有技术的分析数据，难以确定作为调味品完成的判断标准的变化是否来自调味品的变化，即处理容器的内部状况的变化或 来自基于各个虚拟晶片之间的温度变化的另一变化，此外，难以判断调味是否已经完成。 因此，本发明的等离子体处理方法是通过将虚拟晶片W装载到等离子体处理装置1的处理容器2中来进行调味的完成调查的方法，包括：生成预测式 根据预测公式预测调味料的完成情况和进行调味料调查完成情况的另一个过程。 通过对多个测量数据执行多变量分析来实现预测公式的创建，该多个测量数据可以通过首先将虚拟晶片W提供到处理容器2中，冷却处理容器2的内部并提供多个虚拟 晶片W再次进入处理容器2。

公开(公告)号：US20070263456A1

公开(公告)日：2007-11-15

申请号：US11748541

申请日：2007-05-15

Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract translation: NVM阵列包括包括浮动栅极和四晶体管存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

公开(公告)号：US20070257877A1

公开(公告)日：2007-11-08

申请号：US11402800

申请日：2006-04-13

Applicant: Ghy-Bin Wang ,  Hsien-Sheng Huang

Inventor： Ghy-Bin Wang ,  Hsien-Sheng Huang

IPC: G09G3/36 ,  H04L7/00

CPC classification number: H04L7/00 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0275 ,  H04L7/0045 ,  H04L7/005

Abstract: The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream and a sampling module sequentially samples and outputs each signal in the first group signals and the second group signals by the N sampling pulses with a sequence.

Abstract translation: 该方法和电路提供了一个有效的实现来处理多个时钟域之间的数据传输问题。 移位电路移动输入数据流，并且采样模块通过具有序列的N个采样脉冲顺序采样并输出第一组信号和第二组信号中的每个信号。

公开(公告)号：US07263001B2

公开(公告)日：2007-08-28

申请号：US11084213

申请日：2005-03-17

Applicant: Bin Wang ,  Christopher J. Diorio ,  Todd E. Humes

Inventor： Bin Wang ,  Christopher J. Diorio ,  Todd E. Humes

IPC: G11C11/34

CPC classification number: G11C16/24

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.

Abstract translation: NVM阵列包括包括浮动栅极，编程元件和逻辑存储元件的NVM单元的行和列。 在编程或擦除模式期间，每个单元的浮置栅极被充电到预定的电平。 在读取模式开始时，所有存储元件都被预先充电到高电源电压。 在预充电之后，读取所选择的单元以确定存储的位值。 每个单元的浮动栅极的充电状态确定存储元件是否导通，并且预充电电压相应于位值被下拉。

公开(公告)号：US06649486B1

公开(公告)日：2003-11-18

申请号：US09679510

申请日：2000-10-06

Applicant: Subramanian Balakumar ,  Kong Hean Lee ,  Zheng Zhou ,  Xian Bin Wang

Inventor： Subramanian Balakumar ,  Kong Hean Lee ,  Zheng Zhou ,  Xian Bin Wang

IPC: H01L2176

CPC classification number: H01L21/76229

Abstract: A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Abstract translation: 已经实现了制造浅沟槽隔离的新方法。 在半导体衬底上形成焊盘氧化物层。 在衬垫氧化物层上沉积氮化硅层。 覆盖氮化硅层的保护层被沉积。 对保护层，氮化硅层和焊盘氧化物层进行图案化以暴露其中规划浅沟槽隔离的半导体衬底。 蚀刻半导体衬底以形成用于规划的浅沟槽隔离的沟槽。 使用大的沟槽蚀刻角度。 保护层的存在防止在蚀刻期间氮化硅层的损失。 沉积沟槽填充层，覆盖保护层并填充沟槽。 在集成电路器件的制造中，沟槽填充层和保护层被抛光以完成浅沟槽隔离。