公开(公告)号：US11063211B2

公开(公告)日：2021-07-13

申请号：US16201264

申请日：2018-11-27

Applicant: STMicroelectronics S.r.l.

Inventor： Dario Paci ,  Marco Morelli ,  Caterina Riva

IPC: G11B5/127 ,  H04R31/00 ,  H01L43/12 ,  B82Y25/00 ,  G01R33/09 ,  H01L27/22 ,  G01R33/00 ,  H01L43/08 ,  G01R33/02

Abstract: An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

公开(公告)号：US11063027B2

公开(公告)日：2021-07-13

申请号：US16773711

申请日：2020-01-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Davide Giuseppe Patti ,  Mario Antonio Aleo

IPC: H01L23/00 ,  H01L25/16 ,  H01L21/762 ,  H01L21/763 ,  H01L25/00

Abstract: A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.

公开(公告)号：US20210207940A1

公开(公告)日：2021-07-08

申请号：US17207180

申请日：2021-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ZANCANATO ,  Michele FERRAINA ,  Federico RIZZARDINI ,  Stefano Paolo RIVOLTA

IPC: G01B7/30 ,  G06F1/16 ,  G01P15/14 ,  G01P15/18

Abstract: A computing system includes a first hardware element having a first accelerometer and a first gyroscope, and a second hardware element having a second accelerometer and a second gyroscope. The first and second hardware elements are moveable with respect to each other. The computing system recursively generates a result signal indicative of a relative orientation of the first and second hardware elements with respect to each other. The result signal may be generated by generating a first intermediate signal indicative of a angle between the first and second hardware elements based on signals generated by the first and second accelerometers and generating a second intermediate signal indicative of the angle based on signals generated by the first and second gyroscopes. The result signal indicative of the angle may be generated as a weighted sum of the first intermediate signal and the second intermediate signal. At least one of the first and second hardware elements is controlled by on the result signal.

公开(公告)号：US11054319B2

公开(公告)日：2021-07-06

申请号：US17018276

申请日：2020-09-11

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Caltabiano

IPC: G01L1/22 ,  G01B7/16 ,  G01D5/16 ,  G01L1/04 ,  G01L1/06 ,  G01L1/18 ,  G01L19/00 ,  G01L9/04 ,  G01L9/00

Abstract: A semiconductor device includes a strain gauge on a substrate, the strain gauge configured to measure a stress of the substrate; and a temperature sensor disposed within the substrate, the temperature sensor being decoupled from the stress of the substrate.

公开(公告)号：US11049561B2

公开(公告)日：2021-06-29

申请号：US16903264

申请日：2020-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Federico Goller ,  Cesare Torti ,  Marcella Carissimi ,  Emanuela Calvetti

IPC: G11C11/00 ,  G11C13/00

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

公开(公告)号：US20210193220A1

公开(公告)日：2021-06-24

申请号：US17119979

申请日：2020-12-11

Applicant: STMicroelectronics S.r.l.

Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Davide Manfré ,  Cesare Torti

IPC: G11C13/00 ,  G11C7/06 ,  G11C7/02

Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

公开(公告)号：US20210188620A1

公开(公告)日：2021-06-24

申请号：US17126903

申请日：2020-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： Luca SEGHIZZI ,  Nicolo' BONI ,  Laura OGGIONI ,  Roberto CARMINATI ,  Marta CARMINATI

IPC: B81B3/00 ,  B81C1/00

Abstract: For manufacturing an optical microelectromechanical device, a first wafer of semiconductor material having a first surface and a second surface is machined to form a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements which extend between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. A second wafer is machined separately to form a chamber delimited by a bottom wall having a through opening. The second wafer is bonded to the first surface of the first wafer in such a way that the chamber overlies the actuation structure and the through opening is aligned to the suspended mirror structure. Furthermore, a third wafer is bonded to the second surface of the first wafer to form a composite wafer device. The composite wafer device is then diced to form an optical microelectromechanical device.

公开(公告)号：US20210187663A1

公开(公告)日：2021-06-24

申请号：US17121184

申请日：2020-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Antonio BELLIZZI ,  Michele DERAI

IPC: B23K26/38 ,  H01L21/304

Abstract: A semiconductor substrate such as a semiconductor wafer includes a cutting line having a length. The semiconductor substrate is cut along the line by first selectively applying laser beam ablation energy to the semiconductor substrate a certain locations along the cutting line and then blade sawing along cutting line. The semiconductor substrate thus includes one or more ablated regions as well as one or more unablated regions at the cutting line.

公开(公告)号：US20210184576A1

公开(公告)日：2021-06-17

申请号：US17117847

申请日：2020-12-10

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto CATTANI ,  Alessandro GASPARINI

IPC: H02M3/158 ,  H02M1/08 ,  H03K17/06

Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.

公开(公告)号：US20210183849A1

公开(公告)日：2021-06-17

申请号：US17182773

申请日：2021-02-23

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Giuseppe PATTI

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.