CIRCUIT FOR ACCESSING A CHALCOGENIDE MEMORY ARRAY
    411.
    发明申请
    CIRCUIT FOR ACCESSING A CHALCOGENIDE MEMORY ARRAY 有权
    用于访问混合存储器阵列的电路

    公开(公告)号:US20050213367A1

    公开(公告)日:2005-09-29

    申请号:US10811454

    申请日:2004-03-26

    CPC classification number: G11C13/0004 G11C13/0033 G11C13/004 G11C13/0069

    Abstract: A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.

    Abstract translation: 公开了一种用于访问硫族化物存储器阵列的电路。 硫族化物存储器阵列包括具有由硫族化物存储元件形成的行和列的多个子阵列。 硫族化物存储器阵列由离散读和写电路访问。 与各个子阵列相关联,每个写电路包括独立的写0电路和独立的写1电路。 还与相应的一个子阵列相关联,每个读取电路包括读出放大器电路。 此外,电压电平控制模块耦合到读取和写入电路,以确保在读取和写入操作期间跨硫族化物存储器阵列内的硫族化物存储元件的电压不超过预定值。

    Circuit for accessing a chalcogenide memory array
    412.
    发明授权
    Circuit for accessing a chalcogenide memory array 有权
    用于访问硫属化物存储器阵列的电路

    公开(公告)号:US06944041B1

    公开(公告)日:2005-09-13

    申请号:US10811454

    申请日:2004-03-26

    CPC classification number: G11C13/0004 G11C13/0033 G11C13/004 G11C13/0069

    Abstract: A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.

    Abstract translation: 公开了一种用于访问硫族化物存储器阵列的电路。 硫族化物存储器阵列包括具有由硫族化物存储元件形成的行和列的多个子阵列。 硫族化物存储器阵列由离散读和写电路访问。 与相应的一个子阵列相关联,每个写入电路包括独立的写入0电路和独立的写入1电路。 还与相应的一个子阵列相关联,每个读取电路包括读出放大器电路。 此外,电压电平控制模块耦合到读取和写入电路,以确保在读取和写入操作期间跨硫族化物存储器阵列内的硫族化物存储元件的电压不超过预定值。

    Algorithm for multiple-symbol differential detection
    413.
    发明授权
    Algorithm for multiple-symbol differential detection 失效
    多符号差分检测算法

    公开(公告)号:US06842496B2

    公开(公告)日:2005-01-11

    申请号:US10279238

    申请日:2002-10-24

    CPC classification number: H04L27/2331 H04L25/03197 H04L27/2332

    Abstract: A method for differential phase evaluation of M-ary communication data is employed in which the data consists of N sequential symbols r1 . . . rN, each having one of M transmitted phases. Selected sequences of N−1 elements that represent possible sequences of phase differentials are evaluated using multiple-symbol differential detection. Using r1 as the reference for each phase differential estimate, sN−1 phase differential sequences are selected in the form (P2i, P3i, . . . , PNi) for i=1 to s for evaluating said symbol set, where s is predetermined and 1

    Abstract translation: 采用一种用于微分通信数据的差分相位估计的方法,其中数据由N个连续符号r1组成。 。 。 rN,每个都具有M个传输相中的一个。 使用多符号差分检测来评估代表可能的相位差序列的N-1个元素的选定序列。 使用r1作为每个相位差分估计的参考,以i = 1至s的形式(P2i,P3i,...,PNi)选择s 相位差分序列,用于评估所述符号集,其中s 是预定的,1

    Multi-stage receiver
    414.
    发明授权
    Multi-stage receiver 有权
    多级接收机

    公开(公告)号:US06587517B1

    公开(公告)日:2003-07-01

    申请号:US09311708

    申请日:1999-05-13

    Applicant: Bin Li Wen Tong

    Inventor: Bin Li Wen Tong

    Abstract: A multi-stage receiver and method for recovering a traffic signal embedded in at least one received signal. The multi-stage receiver includes a plurality of sequential detection stages for processing each received signal and providing successively better estimates of the traffic signal. The multi-stage receiver includes, for each received signal, a first processing stage and a second processing stage. The multi-stage receiver also includes a final processing stage connected to the second processing stages. Each first processing stage generates a first estimate of the traffic signal from the respective received signal and each second processing stage generates a set of energy values from the respective first estimate of the traffic signal and from the respective received signal. The final processing stage combines the set of energy values from each second processing stage and generates an improved estimate of the traffic signal. By employing multiple stages in the receiver, there is an improvement in successive estimates of the traffic signal.

    Abstract translation: 一种用于恢复嵌入到至少一个接收信号中的业务信号的多级接收机和方法。 多级接收机包括多个顺序检测级,用于处理每个接收到的信号并提供连续更好的业务信号估计。 对于每个接收信号,多级接收机包括第一处理级和第二处理级。 多级接收机还包括连接到第二处理级的最后处理级。 每个第一处理阶段从相应的接收信号产生交通信号的第一估计,并且每个第二处理阶段根据交通信号的相应的第一估计和相应的接收信号产生一组能量值。 最终处理阶段组合来自每个第二处理阶段的能量值集合,并且生成交通信号的改进的估计。 通过在接收机中采用多级,交通信号的连续估计有改善。

    Herbicidal imidazolidinetrione and thioxo-imidazolidinediones
    415.
    发明授权
    Herbicidal imidazolidinetrione and thioxo-imidazolidinediones 失效
    除草咪唑啉四酮和硫代咪唑烷二酮

    公开(公告)号:US06444615B1

    公开(公告)日:2002-09-03

    申请号:US09551345

    申请日:2000-04-18

    Abstract: This invention relates to 1-substituted-phenyl-3-substituted-2-thioxo-4,5-imidazolidinediones and 2,4,5-imidazolidinetriones which have activity as herbicides, to compositions which contain these compounds and to methods of use of these compounds. In particular, the present invention pertains to 2-thioxo-4,5-imidazolidinediones or 2,4,5-imidazolidinetriones wherein a 2,4,5,6-tetrasubstituted phenyl ring is linked to the heterocyclic ring.

    Abstract translation: 本发明涉及具有作为除草剂活性的1-取代苯基-3-取代-2-硫代-4,5-二咪唑烷二酮和含有这些化合物的组合物及其使用方法 化合物。 特别地,本发明涉及2-硫代-4,5-咪唑烷二酮类或2,4,5-咪唑啉四酮,其中2,4,5,6-四取代的苯环与杂环连接。

    Circuit for filtering single event effect (see) induced glitches
    416.
    发明授权
    Circuit for filtering single event effect (see) induced glitches 有权
    用于过滤单个事件效应的电路(见)引起的毛刺

    公开(公告)号:US06392474B1

    公开(公告)日:2002-05-21

    申请号:US09651156

    申请日:2000-08-30

    CPC classification number: H03K5/1252

    Abstract: A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation. By connecting the delay element between the signal input and the second input of the SEE immune latch circuit, a temporal separation greater that the duration of an SEE induced glitch can be achieved on the data being drive into the first and the second inputs of the SEE immune latch circuit. As a result, SEE induced glitches will not be written into the SEE immune latch circuit.

    Abstract translation: 公开了一种用于滤除单事件效应(SEE)引起的毛刺的电路。 SEE诱导毛刺滤波电路包括SEE免疫锁存电路和延迟元件。 SEE免疫锁定电路包括第一输入端,第二输入端和输出端。 只有当具有相同极性的输入输入信号同时在第一输入端和第二输入端同时施加时,SEE免疫锁定器从一个状态改变到另一个状态。 SEE免疫锁定电路的第一个输入直接连接到信号输入,SEE免疫锁存电路的第二个输入端通过延迟元件连接到信号输入端。 延迟元件提供等于或大于SEE诱发毛刺的脉冲宽度但小于在正常操作下的信号输入处的输入信号的预定脉冲宽度的信号延迟时间。 通过连接SEE免疫锁存电路的信号输入和第二输入之间的延迟元件,可以在驱动到SEE的第一和第二输入端的数据上实现SEE引起的毛刺持续时间的时间间隔 免疫锁定电路。 因此,SEE诱发的毛刺不会写入SEE免疫锁定电路。

    Single event upset (SEU) hardened latch circuit
    417.
    发明授权
    Single event upset (SEU) hardened latch circuit 有权
    单事件镦粗(SEU)硬化锁存电路

    公开(公告)号:US06327176B1

    公开(公告)日:2001-12-04

    申请号:US09844079

    申请日:2001-04-26

    CPC classification number: G11C11/4125

    Abstract: A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.

    Abstract translation: 公开了一种单件事件硬化锁定电路。 单事件硬化锁存电路包括第一双端口反相器和第二双端口反相器。 输入端通过第一组通道门耦合到第一双端口逆变器。 第一个双端口逆变器通过第二组通孔连接到第二个双端口逆变器。 输出端连接到第一和第二双端口逆变器。

    Single event upset (SEU) hardened static random access memory cell
    418.
    发明授权
    Single event upset (SEU) hardened static random access memory cell 有权
    单事件镦粗(SEU)硬化静态随机存取存储单元

    公开(公告)号:US06208554B1

    公开(公告)日:2001-03-27

    申请号:US09441942

    申请日:1999-11-17

    CPC classification number: G11C11/4125

    Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The first and second sets of isolation transistors are coupled to the first and second set of cross-coupled transistors, respectively, such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

    Abstract translation: 公开了一种用于静态随机存取存储器的单事件硬化存储单元。 单事件硬化存储单元包括第一组交叉耦合晶体管,第二组交叉耦合晶体管,第一组隔离晶体管和第二组隔离晶体管。 第一和第二组隔离晶体管分别耦合到第一和第二组交叉耦合晶体管,使得在交叉耦合晶体管和隔离晶体管之间形成两个反转路径。

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