Abstract:
A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.
Abstract:
A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.
Abstract:
A method for differential phase evaluation of M-ary communication data is employed in which the data consists of N sequential symbols r1 . . . rN, each having one of M transmitted phases. Selected sequences of N−1 elements that represent possible sequences of phase differentials are evaluated using multiple-symbol differential detection. Using r1 as the reference for each phase differential estimate, sN−1 phase differential sequences are selected in the form (P2i, P3i, . . . , PNi) for i=1 to s for evaluating said symbol set, where s is predetermined and 1
Abstract:
A multi-stage receiver and method for recovering a traffic signal embedded in at least one received signal. The multi-stage receiver includes a plurality of sequential detection stages for processing each received signal and providing successively better estimates of the traffic signal. The multi-stage receiver includes, for each received signal, a first processing stage and a second processing stage. The multi-stage receiver also includes a final processing stage connected to the second processing stages. Each first processing stage generates a first estimate of the traffic signal from the respective received signal and each second processing stage generates a set of energy values from the respective first estimate of the traffic signal and from the respective received signal. The final processing stage combines the set of energy values from each second processing stage and generates an improved estimate of the traffic signal. By employing multiple stages in the receiver, there is an improvement in successive estimates of the traffic signal.
Abstract:
This invention relates to 1-substituted-phenyl-3-substituted-2-thioxo-4,5-imidazolidinediones and 2,4,5-imidazolidinetriones which have activity as herbicides, to compositions which contain these compounds and to methods of use of these compounds. In particular, the present invention pertains to 2-thioxo-4,5-imidazolidinediones or 2,4,5-imidazolidinetriones wherein a 2,4,5,6-tetrasubstituted phenyl ring is linked to the heterocyclic ring.
Abstract:
A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation. By connecting the delay element between the signal input and the second input of the SEE immune latch circuit, a temporal separation greater that the duration of an SEE induced glitch can be achieved on the data being drive into the first and the second inputs of the SEE immune latch circuit. As a result, SEE induced glitches will not be written into the SEE immune latch circuit.
Abstract:
A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.
Abstract:
A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The first and second sets of isolation transistors are coupled to the first and second set of cross-coupled transistors, respectively, such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
Abstract:
Various systems and methods for implementing computational storage are described herein. An orchestrator system is configured to: receive, at the orchestrator system, a registration package, the registration package including function code, a logical location of input data for the function code, and an event trigger for the function code, the event trigger set to trigger in response to when the input data is modified; interface with a storage service, the storage service to monitor the logical location of the input data and notify a location service when the input data is modified; interface with the location service to obtain a physical location of the input data, the location service to resolve the physical location from the logical location of the input data; and configure the function code to execute near the input data
Abstract:
Innovations in encoder-side decisions that use the results of hash-based block matching when setting parameters are presented. For example, some of the innovations relate to ways to select motion vector precision depending on the results of hash-based block matching. Other innovations relate to ways to selectively disable sample adaptive offset filtering depending on the results of hash-based block matching. Still other innovations relate to ways to select which reference pictures to retain in a reference picture set depending on the results of hash-based block matching.