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    Circuit adjustable after packaging having a voltage limiter and method of adjusting same
    422.
    发明授权
    Circuit adjustable after packaging having a voltage limiter and method of adjusting same 有权
    具有限压器的封装后的电路可调节器及其调节方法

    公开(公告)号：US07999597B2

    公开(公告)日：2011-08-16

    申请号：US12470205

    申请日：2009-05-21

    Applicant: Sébastien Laville ,  Frédéric Goutti

    Inventor： Sébastien Laville ,  Frédéric Goutti

    IPC: H03L5/00

    CPC classification number: H01L23/5252 ,  G11C5/143 ,  G11C2207/2254 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.

    Abstract translation: 包装后可调节的电路包括提供有功率电位和参考电位的功能电路，并且具有通过编程至少一个可编程元件和电路来编程功能电路的可编程元件的至少一个参数可调整。 可调节电路还包括限制电路，用于将电源电位和参考电位之间的电压限制到可调节的限制电压，以及调节极限电压的电路。 调整功能电路的参数后，调节限幅电路的极限电压。

    Image deinterlacing
    423.
    发明授权
    Image deinterlacing 有权
    图像去隔行

    公开(公告)号：US07991246B2

    公开(公告)日：2011-08-02

    申请号：US11855936

    申请日：2007-09-14

    Applicant: Jerome Roussel ,  Pascal Bertolino ,  Marina Nicolas

    Inventor： Jerome Roussel ,  Pascal Bertolino ,  Marina Nicolas

    IPC: G06K9/32 ,  H04N7/01

    CPC classification number: G06T3/4007 ,  H04N7/012

    Abstract: Method and devices are provided for processing an image in which a row of pixels with associated light intensity values successively alternates with a row of pixels to which values are to be associated. In each current row of pixels with associated values, pixels are selected which satisfy a selection rule based on the values for the pixels in the current row with associated values and on the values from the previous and/or the next row with associated values, and segments of pixels are detected. In this manner a set of segments is obtained relative to the image being processed, from which a graph of segments is created by linking the segments according to a linking rule. Then the respective values to be associated with at least some of the pixels in the rows to be assigned values are determined by interpolation from segments in the graph which form a path in the graph.

    Abstract translation: 提供了用于处理图像的方法和装置，其中具有相关联的光强度值的像素行连续地与要与其相关联的像素行交替。 在具有相关值的每个当前行像素中，选择满足基于具有相关值的当前行中的像素的值以及来自具有关联值的先前和/或下一行的值的选择规则的像素，以及 检测像素段。 以这种方式，相对于正在处理的图像获得一组段，通过根据链接规则链接段来创建段的图形。 然后，通过对在图中形成图中的路径的图中的段进行插值来确定要与要分配值的行中的至少一些像素相关联的各个值。

    Inductance with a small surface area and with a midpoint which is simple to determine
    424.
    发明授权
    Inductance with a small surface area and with a midpoint which is simple to determine 有权
    具有较小表面积和中点的电感，可以很容易地确定

    公开(公告)号：US07982571B2

    公开(公告)日：2011-07-19

    申请号：US12179847

    申请日：2008-07-25

    Applicant: Frédéric Gianesello

    Inventor： Frédéric Gianesello

    IPC: H01F5/00 ,  H01F27/28

    CPC classification number: H01F17/0013 ,  H01F21/12 ,  H01F27/34 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An inductance formed in a stack of insulating layers, the inductance comprising first and second access terminals and first and second half-loops distributed in the stack of insulating layers on a number of distinct levels greater than or equal to four. For each level, each first half-loop is at least partly symmetrical to one of the second half-loops. All the first half-loops are series-connected according to a first succession of first half-loops to form first loops between the first access terminal and a midpoint and all the second half-loops are series-connected according to a second succession of second half-loops to form second loops between the second output terminal and the midpoint.

    Abstract translation: 电感形成在一叠绝缘层中，该电感包括第一和第二接入端以及分布在绝缘层堆叠中的第一和第二半环，其数量大于或等于四个。 对于每个级别，每个第一半环至少部分地与第二半环中的一个对称。 所有第一半环根据第一连续的第一半环串联连接，以在第一接入终端和中点之间形成第一环路，并且所有第二半环路根据第二连续的第二连续序列连接 半环形成第二输出端和中点之间的第二环。

    Balun with a 1/4 impedance ratio
    426.
    发明授权
    Balun with a 1/4 impedance ratio 有权
    巴伦具有1/4阻抗比

    公开(公告)号：US07952458B2

    公开(公告)日：2011-05-31

    申请号：US11605897

    申请日：2006-11-29

    Applicant: Hilal Ezzeddine

    Inventor： Hilal Ezzeddine

    IPC: H01F5/00 ,  H01F27/28 ,  H01L27/08

    CPC classification number: H01F17/0013 ,  H03H7/42

    Abstract: A mode-switching transformer with a 1-to-4 impedance ratio having a first planar winding formed in a first conductive level from a first differential mode terminal outside of the winding; a second planar winding formed in a second conductive level from a second differential mode terminal outside of the winding; a via of interconnection of the central ends of the first and second windings intended to be connected to ground; and at least one third planar winding in one of the two conductive levels, interdigited with the first or the second winding from a first common-mode terminal outside of the winding, the internal end of the third winding being connected to the via for direct grounding.

    Abstract translation: 一种具有1比4阻抗比的模式切换变压器，其具有从绕组外部的第一差分模式端子形成在第一导电电平中的第一平面绕组; 从绕组外部的第二差分模式端子形成在第二导电电平中的第二平面绕组; 用于连接到地面的第一和第二绕组的中心端的互连通孔; 以及在两个导电电平之一中的至少一个第三平面绕组，与来自绕组外部的第一共模端子与第一或第二绕组交叉，第三绕组的内部端连接到用于直接接地的通孔 。

    Active semiconductor component with a reduced surface area
    428.
    发明授权
    Active semiconductor component with a reduced surface area 有权
    活性半导体元件具有减小的表面积

    公开(公告)号：US07939887B2

    公开(公告)日：2011-05-10

    申请号：US12632641

    申请日：2009-12-07

    Applicant: Jean-Luc Morand

    Inventor： Jean-Luc Morand

    IPC: H01L29/32 ,  H01L29/74

    CPC classification number: H01L29/417 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/861

    Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

    Abstract translation: 一种半导体部件，其中有源接合部基本上横跨其整个厚度垂直于半导体芯片的表面延伸。 与要连接的区域的触点由导电指状物提供，其基本上与要建立触点的整个区域交叉。

    Secure identification with biometric data
    429.
    发明授权
    Secure identification with biometric data 有权
    使用生物特征数据进行安全识别

    公开(公告)号：US07937590B2

    公开(公告)日：2011-05-03

    申请号：US10242519

    申请日：2002-09-12

    Applicant: Luc Wuidart

    Inventor： Luc Wuidart

    IPC: G06F21/00

    CPC classification number: G06F21/32 ,  G07C9/00087 ,  G07C2009/00095

    Abstract: A secure method and device of identification by biometric data in which digital biometric data obtained by a sensor are combined with an identifier of an integrated circuit chip contained in a device common to the sensor.

    Abstract translation: 一种通过生物统计学数据识别的安全方法和装置，其中由传感器获得的数字生物特征数据与包含在传感器公共的装置中的集成电路芯片的标识符组合。

    SEMICONDUCTOR DEVICE COMPRISING AN ELECTROMAGNETIC WAVEGUIDE
    430.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING AN ELECTROMAGNETIC WAVEGUIDE 有权
    包含电磁波的半导体器件

    公开(公告)号：US20110084398A1

    公开(公告)日：2011-04-14

    申请号：US12896558

    申请日：2010-10-01

    Applicant: Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

    Inventor： Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

    IPC: H01L23/48

    CPC classification number: H01P3/121 ,  H01P1/207 ,  H01P5/107

    Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.

    Abstract translation: 半导体器件包括衬底。 在该基板的至少一个面上形成集成电路。 还包括至少一个电磁波导，该波导包括两个金属板，这两个金属板被放置在基板厚度的至少一部分的任一侧上并且彼此相对定位。 两个纵向壁彼此相对地放置并且由在其厚度方向上穿过基板的孔中形成的金属通孔形成。 金属通孔电连接两个金属板。

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