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公开(公告)号：US10725959B2
公开(公告)日：2020-07-28
申请号：US16298373
申请日：2019-03-11
Applicant: Analog Devices Global Unlimited Company
Inventor： David Aherne , Jofrey Santillan , Wes Vernon Lofamia , Paul O'Sullivan , Padraig McDaid
Abstract: SPI Round Robin Mode for Single-Cycle MUX Channel Sequencing. SPI round robin mode is an SPI mode applicable for MUX devices control. It allows the MUX output to connect to the next input channel sequentially in just one clock cycle. Configurations can be made such as: clock edge to use (rising/falling), ascending/descending channel sequence, and enabling/disabling the channels to go through. The device supersedes an ADC with built in sequencing and is applicable to multiplexing, switching, instrumentation, process control and isolation application—while retaining SPI device control and operation.
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公开(公告)号：US20200162076A1
公开(公告)日：2020-05-21
申请号：US16193649
申请日：2018-11-16
Applicant: Analog Devices Global Unlimited Company
Inventor： Alan Patrick Cahill , Michal Brychta , Patrick C. Kirby
Abstract: Techniques for mixing, or modulating, a high-frequency, digital communication signal with a low-frequency, analog current loop signal are provided. In certain examples, the techniques allow mixing the signals in a non-AC coupled manner. In certain examples, such mixing techniques can allow for simplified connections between a modem chip and an analog current loop interface chip of an analog I/O module.
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公开(公告)号：US20200154293A1
公开(公告)日：2020-05-14
申请号：US16186758
申请日：2018-11-12
Applicant: Analog Devices Global Unlimited Company
Inventor： Cornelius O'Mahony , MIchael O'Brien , Andre Wolokita , Gina Aquilano , Sean Williams
IPC: H04W24/08
Abstract: A wireless communication system includes at least one transmitter and at least one receiver. The transmitter is configured to establish wireless link parameters and transmit a data communication using the wireless link parameters. The receiver is configured to receive the data communication, automatically identify one or more of the wireless link parameters using the data, and extract a payload using the identified wireless link parameters. Prior to receiving the data communication, the receiver requires limited information concerning the wireless link parameters established by the transmitter. The wireless link parameters can include selectable aspects such as one or more of a transmission channel, a transmission data rate, a modulation format, a transmission power, a packet format, and a channel coding scheme.
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公开(公告)号：US20200021776A1
公开(公告)日：2020-01-16
申请号：US16175101
申请日：2018-10-30
Applicant: Analog Devices Global Unlimited Company
Inventor： John CULLINANE , Pablo Ventura , Niall D. O'Connell , Isaac Molina Hernandez
Abstract: Disclosed herein are systems and methods for performing SAG effect compensation on a video signal received over an AC-coupled video link. In one aspect, a method for performing SAF effect compensation includes applying a filter to the received video signal to generate a corrected video signal, where a transfer function of the filter is dependent on a transmission parameter that is based on a plurality of parameters of the AC-coupled link. The method further includes extracting predefined content from the corrected video signal, and adjusting the transmission parameter based on a comparison of the extracted predefined content with certain expected content, so that adjusted transmission parameter can be used for one or more subsequent applications of the filter, thereby realizing an adaptive filter.
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公开(公告)号：US20200021305A1
公开(公告)日：2020-01-16
申请号：US16032752
申请日：2018-07-11
Applicant: Analog Devices Global Unlimited Company
Inventor： Sandeep Monangi
Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
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Patent Agency Ranking
公开(公告)号：US10523016B2
公开(公告)日：2019-12-31
申请号：US15146616
申请日：2016-05-04
Applicant: Analog Devices Global
Inventor： Stefan Hacker , Andreas Koch , Ralph Patrick McCormick
Abstract: An apparatus is provided comprising: a first power domain that includes a first component that operates at a first voltage level; a second power domain that includes a media access controller (MAC) that operates at a second voltage level; and a third power domain that includes a physical media access (PHY) device that operates at a third voltage level; wherein the first voltage level is higher than the second voltage level; and wherein the second voltage level is unreferenced; further including: a first reinforced electrical isolation circuit disposed on a first circuit path that includes at least one signal lane that extends between the first power domain and the second power domain; and a second reinforced electrical isolation circuit disposed on a second circuit path that includes at least one signal lane that extends between the MAC device and the PHY device.
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公开(公告)号：US10521939B2
公开(公告)日：2019-12-31
申请号：US13896105
申请日：2013-05-16
Applicant: Analog Devices Global Unlimited Company
Inventor： Himanshu Srivastava
IPC: G06T11/60
Abstract: An apparatus includes a processing unit that divides an overlay buffer into a plurality of macro blocks, draws a graphic primitive object including a plurality of pixels, identifies one of the plurality of macro blocks upon a determination that the plurality of pixels has crossed a boundary of the one of the plurality of macro blocks, and image processes the one of the plurality of macro blocks.
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公开(公告)号：US10516411B1
公开(公告)日：2019-12-24
申请号：US16032752
申请日：2018-07-11
Applicant: Analog Devices Global Unlimited Company
Inventor： Sandeep Monangi
Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
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公开(公告)号：US10516408B2
公开(公告)日：2019-12-24
申请号：US15916009
申请日：2018-03-08
Applicant: Analog Devices Global Unlimited Company
Inventor： Rares Bodnar , Asif Ahmad , Christopher Peter Hurrell
Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.
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公开(公告)号：US20190386643A1
公开(公告)日：2019-12-19
申请号：US16010219
申请日：2018-06-15
Applicant: Analog Devices Global Unlimited Company
Inventor： David SAYAGO , Thomas F. ROCHE , John A. CLEARY
Abstract: The present disclosure provides a pulse generator which generates a pulse train by mixing pulses of a first clock having a first frequency, with pulses of a second clock having a second frequency. Over a predefined time period, the combination of pulses results in a pulse train having an effective frequency which is between the first and second frequencies. A multiplexer is used to select which of the first and second clocks should be provided to the output. Depending on the desired target frequency, the multiplexer is controlled to mix differing amounts of pulses from the first and second clocks. A multiplexer is controlled by a control signal, which is generated using combinatorial logic using the first clock as an input. The pulse generator may be used, for example, as a clock for a charge pump.
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