公开(公告)号：US20210235107A1

公开(公告)日：2021-07-29

申请号：US16775463

申请日：2020-01-29

Applicant: Mellanox Technologies, Ltd. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Tamar Shoham

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/177

Abstract: A video processor includes a memory and a processor. The processor is coupled to memory and is configured to store in the memory (i) multiple raw frames belonging to a Group of Pictures (GOP) to be processed, and (ii) one or more reference frames. The processor is further configured to select for multiple target blocks having a same block-location in respective raw frames associated with a common reference frame, a common search region in the common reference frame, and before selecting another search region, to apply at least two motion estimation operations using at least two of the target blocks and the common search region, to estimate respective at least two Motion Vectors (MVs).

公开(公告)号：US20210203610A1

公开(公告)日：2021-07-01

申请号：US17204968

申请日：2021-03-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin ,  Haggai Eran ,  Adi Menachem

IPC: H04L12/833 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08 ,  H04L12/851 ,  H04L12/413 ,  H04L12/00

Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.

公开(公告)号：US20210184432A1

公开(公告)日：2021-06-17

申请号：US17247401

申请日：2020-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuri Berk ,  Vladimir Iakovlev ,  Tamir Sharkaz ,  Elad Mentovich

IPC: H01S5/183 ,  H01S5/227

Abstract: A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a mesa structure disposed on a substrate. The mesa structure defines an emission axis of the VCSEL. The mesa structure includes a first reflector, a second reflector, and a cascaded active region structure disposed between the first reflector and the second reflector. The cascaded active region structure includes a plurality of cascaded active region layers disposed along the emission axis, where each of the cascade active region layers includes an active region having multi-quantum well and/or dots layers (MQLs), a tunnel junction aligned with the emission axis, and an oxide confinement layer. The oxide confinement layer is disposed between the tunnel junction and MQLs, and has an electrical current aperture defined therein. The mesa structure defines an optical window through which the VCSEL is configured to emit light.

公开(公告)号：US11031939B1

公开(公告)日：2021-06-08

申请号：US16823577

申请日：2020-03-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Omer Wolkovitz ,  Eilon Yanai

IPC: H03L7/08 ,  H03L7/091

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.

公开(公告)号：US20210152484A1

公开(公告)日：2021-05-20

申请号：US16683302

申请日：2019-11-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Shpigelman ,  Roee Moyal ,  Shahrazad Hleihel ,  Kobi Pines

IPC: H04L12/825 ,  H04L12/841 ,  H04L12/823

Abstract: A network adapter includes a receive (RX) pipeline, a transmit (TX) pipeline, hardware-implemented congestion-control circuitry, and a congestion-control processor. The RX pipeline is configured to receive packets from a network and process the received packets. The TX pipeline is configured to transmit packets to the network. The hardware-implemented congestion-control circuitry is configured to receive, from the TX pipeline and from the RX pipeline, Congestion-Control (CC) events derived from at least some of the packets transmitted to the network and from at least some of the packets received from the network, and to pre-process the CC events. The congestion-control processor is configured to receive the pre-processed CC events from the congestion-control circuitry, and to throttle a transmission rate of the packets transmitted to the network by the TX pipeline responsively to the pre-processed CC events.

公开(公告)号：US10958627B2

公开(公告)日：2021-03-23

申请号：US16858874

申请日：2020-04-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Adi Menachem ,  Liran Liss ,  Boris Pismenny

IPC: H04L29/06 ,  G06F21/60 ,  G06F21/53 ,  H04L9/08 ,  G06F9/455 ,  H04L9/14 ,  H04L9/32

Abstract: Computing apparatus includes a host processor, which runs a virtual machine monitor (VMM), which supports a plurality of virtual machines and includes a cryptographic security software module. A network interface controller (NIC) links the host processor to a network so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module, which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.

公开(公告)号：US10855331B1

公开(公告)日：2020-12-01

申请号：US16685400

申请日：2019-11-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Anna Sandomirsky ,  Itshak Kalifa ,  Boaz Atias ,  Eyal Babish

IPC: H04B3/00 ,  H04L25/00 ,  H04B3/02 ,  H01R13/66 ,  H01B1/02

Abstract: Apparatuses, systems, and associated methods are described that provide signal transmission over copper media. An example module includes a number of electrical signal generators that each generate an electrical signal, and a signal modulation system that receives the electrical signals generated by the electrical signal generators. The signal modulation system further modulates each of the electrical signals such that each modulated electrical signal is distinguishable from the other modulated electrical signals. The module further includes an active copper multiplexer in electrical communication with the electrical signal generators that receives the modulated electrical signals from the signal modulation system. The active copper multiplexer further combines the multiple modulated signals into a single combined electrical signal and transmits the single combined electrical signal through a single copper cable.

公开(公告)号：US20200371708A1

公开(公告)日：2020-11-26

申请号：US16416290

申请日：2019-05-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Karin Karmani ,  Lion Levi ,  Zachy Haramaty ,  Ran Shani

IPC: G06F3/06 ,  H04L12/861

Abstract: A network element including buffer address control circuitry for reading a given entry from a queue in a memory of a device external to the network element, the queue having at least a first entry and a last entry, the given entry including a destination address in the memory, output circuitry for writing data included in a packet received from external to the network element to the destination address in the memory in accordance with the given entry, and next entry assignment circuitry for assigning a next entry by: when the given entry is other than the last entry in the first queue, assigning the next entry to be an entry in the first queue after the given entry, and when the given entry is the last entry in the first queue, assigning the next entry to be the first entry in the first queue. Related apparatus and methods are also described.

公开(公告)号：US10834006B2

公开(公告)日：2020-11-10

申请号：US16255863

申请日：2019-01-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Moni Levy ,  Sagi Rotem

IPC: H04L12/823 ,  H04L12/26 ,  H04L12/863 ,  H04L12/859 ,  H04L12/931

Abstract: A method including providing a network switch, including switching circuitry, packet drop decision circuitry, packet duplication circuitry, and packet exporting circuitry, and performing the following in the network switch: switching packets in the switching circuitry, identifying a packet that is to be dropped in the packet drop decision circuitry, duplicating the packet that is to be dropped in the packet duplication circuitry, producing a first packet and a second packet, exporting the first packet to a tail-drop packet buffer in the packet exporting circuitry, and exporting the second packet to a cyclic packet buffer in the packet exporting circuitry. Related apparatus and methods are also provided. The abstract is not intended to be limiting.

公开(公告)号：US10824469B2

公开(公告)日：2020-11-03

申请号：US16202132

申请日：2018-11-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Eitan Hirshberg ,  Ariel Shahar ,  Najeeb Darawshy ,  Omri Kahalon

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.