公开(公告)号：US20230136742A1

公开(公告)日：2023-05-04

申请号：US18146543

申请日：2022-12-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01R31/317 ,  H01L25/16 ,  G02F1/21 ,  G02B6/28 ,  G02B6/12 ,  G02B6/27 ,  G02B6/293 ,  G01M11/00

Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

公开(公告)号：US11626365B2

公开(公告)日：2023-04-11

申请号：US17226324

申请日：2021-04-09

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US11610933B2

公开(公告)日：2023-03-21

申请号：US17327364

申请日：2021-05-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Lalanne ,  Laurent Gay ,  Pascal Fonteneau ,  Yann Henrion ,  Francois Guyader

IPC: H01L27/146 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306

Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

公开(公告)号：US11609378B2

公开(公告)日：2023-03-21

申请号：US17649520

申请日：2022-01-31

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric Boeuf ,  Luca Maggi

IPC: G02B6/124 ,  G02B6/34 ,  G02B6/43 ,  G02B6/30 ,  G02B6/12 ,  G02B6/136

Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

公开(公告)号：US20230058720A1

公开(公告)日：2023-02-23

申请号：US17885406

申请日：2022-08-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvie DEL MEDICO ,  Jean-Christophe GRENIER ,  Jean-Christophe GIRAUDIN ,  Philippe KOWALCZYK ,  Fausto PIAZZA

IPC: H01L23/00 ,  H01L21/027

Abstract: The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.

公开(公告)号：US20230051672A1

公开(公告)日：2023-02-16

申请号：US17861458

申请日：2022-07-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Harsh RAWAT ,  Praveen Kumar VERMA ,  Promod KUMAR ,  Christophe LECOCQ

IPC: G11C8/10 ,  G11C8/08 ,  G11C7/10 ,  G11C7/22

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

公开(公告)号：US11573260B2

公开(公告)日：2023-02-07

申请号：US17543337

申请日：2021-12-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: G01R31/28

Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.

公开(公告)号：US20230030472A1

公开(公告)日：2023-02-02

申请号：US17869172

申请日：2022-07-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Axel CROCHERIE ,  Olivier LE-BRIZ

IPC: H01L27/146

Abstract: An optical sensor includes pixels, with each pixel formed by a photodetector and a telecentric system topping the photodetector. Each telecentric system includes: an opaque layer with openings facing the photodetector and a microlens facing each opening and arranged between the opaque layer and the photodetector. Each pixel further includes an optical filter between the microlenses and the photodetector. The optical filter may, for example, be an interference filter, a diffraction grating-based filter or a metasurface-based filter.

公开(公告)号：US20230015854A1

公开(公告)日：2023-01-19

申请号：US17932623

申请日：2022-09-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Francois CARPENTIER ,  Charles BAUDOT

IPC: G02B6/43 ,  G02B6/12 ,  G02B6/13 ,  G02B6/42

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

公开(公告)号：US20220406828A1

公开(公告)日：2022-12-22

申请号：US17840342

申请日：2022-06-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Axel CROCHERIE ,  Sandrine VILLENAVE ,  Felix BARDONNET

IPC: H01L27/146 ,  G02B27/42

Abstract: The present disclosure relates to an image sensor comprising a first layer of photoelectric material and a diffraction grating located between said first layer and the face of the sensor configured to receive light rays.