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公开(公告)号:US20190341114A1
公开(公告)日:2019-11-07
申请号:US16511703
申请日:2019-07-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor: François Tailliet , Marc Battista
Abstract: A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words. The B-1 second electrically-conducting links are disposed above the first plane and physically extend at least partially over at least two memory words of the memory words.
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公开(公告)号:US10454530B2
公开(公告)日:2019-10-22
申请号:US16102068
申请日:2018-08-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Tramoni
Abstract: A near-field communication circuit includes an oscillating circuit having a controllable capacitor. A control circuit is coupled to the oscillating circuit to control the controllable capacitor. A battery is coupled to the control circuit to enable control when the near-field communication circuit is in a standby mode. The near-field communication circuit can be utilized by a mobile communication device.
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公开(公告)号:US20190312088A1
公开(公告)日:2019-10-10
申请号:US16375571
申请日:2019-04-04
Inventor: Philippe BOIVIN , Jean Jacques FAGOT , Emmanuel PETITPREZ , Emeline SOUCHIER , Olivier WEBER
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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公开(公告)号:US20190312087A1
公开(公告)日:2019-10-10
申请号:US16375557
申请日:2019-04-04
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Philippe BOIVIN
IPC: H01L27/24 , H01L45/00 , H01L27/082 , H01L29/10 , H01L21/8222
Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.
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公开(公告)号:US10440575B2
公开(公告)日:2019-10-08
申请号:US15723917
申请日:2017-10-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Charles
Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.
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公开(公告)号:US20190287862A1
公开(公告)日:2019-09-19
申请号:US16429836
申请日:2019-06-03
Inventor: Benoit FROMENT , Stephan NIEL , Arnaud REGNIER , Abderrezak MARZAKI
IPC: H01L21/8234 , H01L49/02 , H01L21/762 , H01L27/08 , H01C7/12 , H01L21/74 , H01L29/8605 , H01L29/06 , H01L23/522 , H01L21/765
Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
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487.
公开(公告)号:US20190279947A1
公开(公告)日:2019-09-12
申请号:US16292958
申请日:2019-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Abderrezak MARZAKI , Mathieu LISART
Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
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公开(公告)号:US20190268040A1
公开(公告)日:2019-08-29
申请号:US16277678
申请日:2019-02-15
Inventor: Gwenael Maillet , Jean-Louis Labyre , Gilles Bas
Abstract: A circuit includes a near-field communication circuit configured to receive a radio frequency control signal transmitted in a near-field regime, a pulse width modulation signal generation circuit coupled to the near-field communication circuit circuit and configured to generate a pulse width modulation signal according to the radio frequency control signal, and a non-volatile memory coupled to both the near-field communication circuit circuit and the pulse width modulation signal generation circuit, the non-volatile memory comprising digital words for configuring the pulse width modulation signal.
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公开(公告)号:US10388695B2
公开(公告)日:2019-08-20
申请号:US13659622
申请日:2012-10-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal Fornara , Christian Rivero
Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.
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公开(公告)号:US20190237141A1
公开(公告)日:2019-08-01
申请号:US16256525
申请日:2019-01-24
Inventor: Francesco LA ROSA , Marc MANTELLI , Stephan NIEL , Arnaud REGNIER
Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
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