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    Storage drive with multiple controllers having interconnected buffer managers
    481.
    发明授权
    Storage drive with multiple controllers having interconnected buffer managers 有权

    公开(公告)号：US10042785B1

    公开(公告)日：2018-08-07

    申请号：US15689414

    申请日：2017-08-29

    Applicant: Seagate Technology LLC

    Inventor： Bruce Douglas Buch ,  Paul Michael Wiggins

    IPC: G11C19/00 ,  G06F13/16 ,  G06F13/38 ,  G06F3/06 ,  G06F12/0831

    Abstract: A data storage device includes first and second controllers that independently and simultaneously process data from a recording medium. The first and second controllers each have respective first and second buffer managers coupled to respective first and second buffer memories. The first and second buffer managers are coupled to each other via an inter-controller data bus. The first controller is configured to receive a contiguous memory request for a block data transfer client of the first controller. A first part of the request is fulfilled from the first buffer memory via the first buffer manager, and a second part of the request is fulfilled from the second buffer memory via the second buffer manager communicating with the first buffer manager via the inter-controller data bus.

    HEAT ASSISTED RECORDING MEDIA INCLUDING MUTLI-LAYER GRANULAR HEATSINK
    482.
    发明申请
    HEAT ASSISTED RECORDING MEDIA INCLUDING MUTLI-LAYER GRANULAR HEATSINK 审中-公开

    公开(公告)号：US20180218752A1

    公开(公告)日：2018-08-02

    申请号：US15422379

    申请日：2017-02-01

    Applicant: Seagate Technology LLC

    Inventor： Bin LU ,  Yingguo PENG ,  Jan-Ulrich THIELE

    IPC: G11B5/73 ,  G11B5/84 ,  G11B5/851 ,  G11B5/667

    CPC classification number: G11B5/7325 ,  G11B5/66

    Abstract: Provided herein is a method including depositing an amorphous magnetic soft underlayer (SUL) over a substrate. A first portion of a heatsink layer is deposited over the SUL, wherein the first portion includes first heat conductive grains that are separated by first grain boundaries. A second portion of the heatsink layer is deposited over the first portion, wherein the second portion includes second heat conductive grains that are separated by second grain boundaries. The second grain boundaries are thicker than the first grain boundaries. A third portion of the heatsink layer is deposited over the second portion, wherein the third portion includes third heat conductive grains that are separated by third grain boundaries. The third grain boundaries are thicker than the second grain boundaries. A granular recording layer is deposited over the heatsink layer.

    Read cache management
    486.
    发明授权
    Read cache management 有权

    公开(公告)号：US10037149B2

    公开(公告)日：2018-07-31

    申请号：US15185497

    申请日：2016-06-17

    Applicant: Seagate Technology LLC

    Inventor： Alexey V. Nazarov ,  Andrew Michael Kowles

    IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0871

    CPC classification number: G06F3/0611 ,  G06F3/0641 ,  G06F3/0656 ,  G06F3/068 ,  G06F12/0871

    Abstract: Implementations disclosed herein provide for a storage system including an on-disk read cache and a variety of read cache management techniques. According to one implementation, a storage device controller time-sequentially reads a series of non-contiguous data blocks storing a data sequence in a read cache of a magnetic disk, the data sequence identified by a requested sequence of logical block addresses (LBAs). The controller determines that read requests for the data sequence satisfy at least one predetermined access frequency criterion and, responsive to the determination, the controller re-writes data of the data sequence to a series of contiguous data blocks in the read cache.

    Planar expansion card assembly
    489.
    发明授权
    Planar expansion card assembly 有权

    公开(公告)号：US10028402B1

    公开(公告)日：2018-07-17

    申请号：US15466391

    申请日：2017-03-22

    Applicant: Seagate Technology LLC

    Inventor： Robert Irving Walker

    IPC: H01R12/00 ,  H05K7/14 ,  H01R12/72 ,  H01R12/73 ,  H01R43/26

    Abstract: The disclosed technology includes an assembly of two planar expansion card cards, which provides functionality to be leveraged by an upper planar expansion card. The base planar expansion card includes a first connector A, a first connector B, a connector C, a first pass-through connector A configured to connect to the first connector A, and a first pass-through connector B configured to connect to the first connector B. An upper planar expansion card includes a second connector A and a second connector B. The second connector A and the second connector B connect to the first pass-through connector A and the first B connector pass-through, respectively. In some implementations, the second connector A and second connector B are configured for a PCI-E and the connector C is configured for Ethernet KR signals.

    Decoupled locking DMA architecture
    490.
    发明授权
    Decoupled locking DMA architecture 有权

    公开(公告)号：US10025735B2

    公开(公告)日：2018-07-17

    申请号：US14161290

    申请日：2014-01-22

    Applicant: Seagate Technology LLC

    Inventor： Earl T Cohen ,  Timothy Lawrence Canepa

    IPC: G06F13/28

    Abstract: A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.

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