公开(公告)号：US09582431B2

公开(公告)日：2017-02-28

申请号：US14158380

申请日：2014-01-17

Applicant: Seagate Technology LLC

Inventor： Earl T Cohen

IPC: G06F12/1009 ,  G06F12/10 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/217 ,  G06F2212/262 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: Storage address space to NVM address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping function to convert a logical block address from a host to an address of a smallest read unit of the NVM. The mapping function provides span and length information corresponding to the logical block address. The span information specifies a number of contiguous smallest read units to read to provide data (corresponding to the logical block address) to the host. The length information specifies how much of the contiguous smallest read units relate to the data provided to the host. The converted address and the length information are usable to improve recycling of no longer needed (e.g. released) portions of the NVM, and usable to facilitate recovery from outages and/or unintended interruptions of service.

Abstract translation: 存储地址空间到NVM地址，跨度和长度映射/转换由固态存储系统的控制器执行，该固态存储系统包括将逻辑块地址从主机转换为地址的最小读取单元的映射功能 NVM。 映射功能提供对应于逻辑块地址的跨度和长度信息。 跨度信息指定要向主机提供数据（对应于逻辑块地址）的读取的连续最小读取单元的数量。 长度信息指定连续的最小读取单元中的数量与提供给主机的数据相关。 转换的地址和长度信息可用于改善NVM的不再需要（例如发布）部分的再循环，并且可用于便于从中断和/或意外中断的服务中恢复。

公开(公告)号：US09395924B2

公开(公告)日：2016-07-19

申请号：US14158827

申请日：2014-01-19

Applicant: Seagate Technology LLC

Inventor： Earl T Cohen ,  Timothy Lawrence Canepa

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: Management of and region selection for writes to non-volatile memory of an SSD improves performance, reliability, unit cost, and/or development cost of an SSD. A controller receives and determines characteristics of writes (e.g. by analyzing the write data, the write data source, and/or by receiving a hint) and selects a region based on the determined characteristics and properties of regions of non-volatile memory. For example, a controller receives writes determined to be read-only data and selects regions of non-volatile memory containing cells that are likely to have write failures. By placing read-only data in write failure prone regions, the likelihood of an error is reduced, thus improving reliability. As another example, a controller receives writes hinted to be uncompressible and selects regions of non-volatile memory containing uncompressible data.

Abstract translation: 用于写入SSD的非易失性存储器的管理和区域选择提高了SSD的性能，可靠性，单位成本和/或开发成本。 控制器接收并确定写入的特性（例如，通过分析写入数据，写入数据源和/或通过接收提示）并且基于所确定的非易失性存储器区域的特性和属性来选择区域。 例如，控制器接收被确定为只读数据的写入，并且选择包含可能具有写入故障的单元的非易失性存储器的区域。 通过将只读数据放置在写入故障易发区域中，错误的可能性降低，从而提高可靠性。 作为另一示例，控制器接收暗示为不可压缩的写入并且选择包含不可压缩数据的非易失性存储器的区域。

公开(公告)号：US10025735B2

公开(公告)日：2018-07-17

申请号：US14161290

申请日：2014-01-22

Applicant: Seagate Technology LLC

Inventor： Earl T Cohen ,  Timothy Lawrence Canepa

IPC: G06F13/28

Abstract: A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.

公开(公告)号：US09430154B2

公开(公告)日：2016-08-30

申请号：US14472869

申请日：2014-08-29

Applicant: Seagate Technology LLC

Inventor： Earl T Cohen

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0676 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1072 ,  G06F2206/1014 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract translation: 对于从SLC NVM（或MLC的下页）读取的每个读取单元，SSD控制器维持零计数和一个计数，和/或在一些实施例中为零/一个视差计数。 在读取单元部分由于阈值电压分布远离其标称分布的偏移而不能校正的情况下，维持的计数使得能够确定方向和/或幅度以调整读取阈值以跟踪阈值电压 移位并恢复读数据零/一个余额。 在各种实施例中，基于所描述的因素的数量（确定的阈值电压分布，已知存储值，过去的NVM操作事件）以各种描述的方式（计数，百分比）来确定调整的读取阈值。 对于MLC存储器描述了前述技术的扩展。

公开(公告)号：US20150287453A1

公开(公告)日：2015-10-08

申请号：US14687686

申请日：2015-04-15

Applicant: Seagate Technology LLC

Inventor： Yingquan WU ,  Earl T Cohen

IPC: G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

Abstract: An SSD controller dynamically adjust read thresholds in a NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample read thresholds, estimates the device threshold voltage distributions, and adjusts the current read thresholds of the portion to calculated new operating read thresholds of the sub-portion. In a second aspect, the portion includes data with a known statistical average number of zero and/or one bits.

Abstract translation: SSD控制器动态调整NVM中的读取阈值，以减少由于器件阈值电压分配偏移引起的错误，从而提高存储子系统（如SSD）的性能，可靠性和/或成本。 在第一方面，控制器周期性地对NVM的一部分进行离线跟踪。 控制器读取具有当前读取阈值的代表性子部分。 如果读取满足条件，则控制器读取具有采样读取阈值的子部分，估计器件阈值电压分布，并且调整部分的当前读取阈值以计算子部分的新的操作读取阈值。 在第二方面，该部分包括具有已知的统计平均数为零和/或一个比特的数据。

公开(公告)号：US20150205527A1

公开(公告)日：2015-07-23

申请号：US14472869

申请日：2014-08-29

Applicant: Seagate Technology LLC

Inventor： Earl T Cohen

IPC: G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0676 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1072 ,  G06F2206/1014 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract translation: 对于从SLC NVM（或MLC的下页）读取的每个读取单元，SSD控制器维持零计数和一个计数，和/或在一些实施例中为零/一个视差计数。 在读取单元部分由于阈值电压分布远离其标称分布的偏移而不能校正的情况下，维持的计数使得能够确定方向和/或幅度以调整读取阈值以跟踪阈值电压 移位并恢复读数据零/一个余额。 在各种实施例中，基于所描述的因素的数量（确定的阈值电压分布，已知存储值，过去的NVM操作事件）以各种描述的方式（计数，百分比）来确定调整的读取阈值。 对于MLC存储器描述了前述技术的扩展。

公开(公告)号：US09595320B2

公开(公告)日：2017-03-14

申请号：US14687686

申请日：2015-04-15

Applicant: Seagate Technology LLC

Inventor： Yingquan Wu ,  Earl T Cohen

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

Abstract: An SSD controller dynamically adjust read thresholds in a NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample read thresholds, estimates the device threshold voltage distributions, and adjusts the current read thresholds of the portion to calculated new operating read thresholds of the sub-portion. In a second aspect, the portion includes data with a known statistical average number of zero and/or one bits.

Abstract translation: SSD控制器动态调整NVM中的读取阈值，以减少由于器件阈值电压分配偏移引起的错误，从而提高存储子系统（如SSD）的性能，可靠性和/或成本。 在第一方面，控制器周期性地对NVM的一部分进行离线跟踪。 控制器读取具有当前读取阈值的代表性子部分。 如果读取满足条件，则控制器读取具有采样读取阈值的子部分，估计器件阈值电压分布，并且调整部分的当前读取阈值以计算子部分的新的操作读取阈值。 在第二方面，该部分包括具有已知的统计平均数为零和/或一个比特的数据。

公开(公告)号：US09886383B2

公开(公告)日：2018-02-06

申请号：US14611258

申请日：2015-02-01

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Earl T Cohen ,  Timothy L Canepa

IPC: G06F12/0815

CPC classification number: G06F12/0815 ,  G06F11/07 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1032 ,  G06F2212/621 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C16/02 ,  G11C16/06

Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.

公开(公告)号：US20160188405A1

公开(公告)日：2016-06-30

申请号：US14945276

申请日：2015-11-18

Applicant: Seagate Technology LLC

Inventor： Yan Li ,  Hao Zhong ,  Radoslav Danilak ,  Earl T Cohen

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G11C11/56

CPC classification number: G06F11/1068 ,  G06F11/1016 ,  G06F11/1048 ,  G11C11/5628 ,  G11C29/52 ,  H03M13/05 ,  H03M13/2906

Abstract: Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.

Abstract translation: 与闪存一起使用的自适应ECC技术可以改善闪存的使用寿命，可靠性，性能和/或存储容量。 这些技术包括具有各种码率和/或各种码长（提供不同的纠错能力）的ECC方案和错误统计收集/跟踪（例如经由专用的硬件逻辑块）。 所述技术还包括根据ECC方案中的一个或多个的编码/解码，以及至少部分地基于来自错误统计收集/跟踪的信息（例如，经由 硬件逻辑自适应编解码器，从专用误差统计收集/跟踪硬件逻辑块接收输入）。 这些技术还包括随着时间的推移，以各种操作模式（例如，作为MLC页面或SLC页面）选择性地操作闪速存储器的一部分（例如，页面，块）。