公开(公告)号：US20090267046A1

公开(公告)日：2009-10-29

申请号：US12425223

申请日：2009-04-16

Applicant: Pascale Mazoyer ,  Germain Bossu

Inventor： Pascale Mazoyer ,  Germain Bossu

IPC: H01L45/00 ,  H01L21/283

CPC classification number: H01L45/1233 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/14

Abstract: A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the diffusion of metal; a second layer made of porous material on the said first layer; a third layer of metallic material allowing to realize a contact electrode susceptible to spread within the said formed porous material of the second layer. Diffusion of metallic ions within the said second layer is controlled by the joint action of an electric field and temperature. A manufacturing process is also described.

Abstract translation: 存储器结构具有与可编程电阻元件串联的存取晶体管，其中可编程电阻元件包括在半导体衬底上; 具有空腔的绝缘层，包括：衬在所述腔的侧表面和底部并且不可渗透金属的第一层; 在所述第一层上由多孔材料制成的第二层; 第三层金属材料允许实现容易在第二层的所形成的多孔材料内扩散的接触电极。 所述第二层内的金属离子的扩散由电场和温度的联合作用控制。 还描述了制造过程。

公开(公告)号：US07607044B2

公开(公告)日：2009-10-20

申请号：US11509304

申请日：2006-08-23

Applicant: Gerard Humeau ,  Roland Marbot

Inventor： Gerard Humeau ,  Roland Marbot

IPC: G06F11/00

CPC classification number: G06F11/3636

Abstract: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit, comprising at least one serial connection. The monitoring data are serialized within the circuit before being transmitted, then restored within the device for tuning the program.

Abstract translation: 一种用于监视由电子电路的处理器执行程序的方法包括收集电路内的监视数据并将监视数据发送到用于调试程序的设备的操作。 监视数据经由电路外部的连接发送，包括至少一个串行连接。 监控数据在发送之前在电路内串行化，然后在设备内恢复以调谐程序。

公开(公告)号：US07593258B2

公开(公告)日：2009-09-22

申请号：US11641550

申请日：2006-12-19

Applicant: Pierre-Yvan Liardet ,  Yannick Teglia ,  Alain Pomet

Inventor： Pierre-Yvan Liardet ,  Yannick Teglia ,  Alain Pomet

IPC: G11C11/34

CPC classification number: G06F21/75 ,  G06F21/755 ,  G06F21/77

Abstract: A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection and, in a way independent in time from the detection, intervening upon the non-volatile memory according to the value of said variable.

Abstract translation: 一种用于保护包括至少一个非易失性存储器的集成电路的方法，包括以下步骤：检测由集成电路执行的程序的流动中可能的干扰，修改易失性存储元件中的数字变量的值 干扰检测的情况，并且以与检测不同的时间独立的方式，根据所述变量的值插入在非易失性存储器上。

公开(公告)号：US20090212330A1

公开(公告)日：2009-08-27

申请号：US12372415

申请日：2009-02-17

Applicant: Emilie Bernard ,  Bernard Guillaumot ,  Philippe Coronel

Inventor： Emilie Bernard ,  Bernard Guillaumot ,  Philippe Coronel

IPC: H01L29/772 ,  H01L21/3205

CPC classification number: H01L29/4908 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/78696

Abstract: A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.

Abstract translation: 半导体器件包括半导体沟道区和栅极区。 栅极区域具有在沟道区域下方延伸的至少一个掩埋部分。 栅极区域的掩埋部分通过在沟道区域下形成空腔而形成。 该空腔至少部分地被硅和金属填充。 进行退火步骤以在腔中形成所述金属的硅化物。 结果是用于半导体器件的完全硅化掩埋栅极。

公开(公告)号：US07573141B2

公开(公告)日：2009-08-11

申请号：US10961466

申请日：2004-10-08

Applicant: Jérôme Lopez

Inventor： Jérôme Lopez

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3677 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A semiconductor package includes a support plate made of an electrically non-conducting material. Electrical connection vias are formed outside a chip fixing region provided on the front face of the support plate. Electrical connection wires connect pads on a front of the chip to pads on the front of the support plate associated with the electrical connection vias. The front face of the support plate is further provided with at least one intermediate front layer made of a thermally conducting material extending at least partly below the chip. The rear face of the support plate is provided with at least one rear layer made of a thermally conducting material extending at least partly opposite the front layer. The front and rear layers are connected by vias made of a thermally conducting material that fills through-holes made through the plate.

Abstract translation: 半导体封装包括由不导电材料制成的支撑板。 电连接通孔形成在设置在支撑板的前表面上的芯片固定区域的外部。 电气连接线将芯片前部的焊盘连接到与电气连接通孔相关联的支撑板前部的焊盘。 支撑板的前表面还设置有至少一个由至少部分地在芯片下方延伸的导热材料制成的中间前层。 支撑板的后表面设置有至少一个由至少部分地与前层相对延伸的导热材料制成的后层。 前层和后层通过由导热材料制成的通孔连接，填充通过板制成的通孔。

公开(公告)号：US07567464B2

公开(公告)日：2009-07-28

申请号：US11654383

申请日：2007-01-15

Applicant: Philippe Gendrier ,  Philippe Candelier ,  Jean-Marc Tessier

Inventor： Philippe Gendrier ,  Philippe Candelier ,  Jean-Marc Tessier

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G06F11/1008 ,  G11C16/3431 ,  G11C16/3459 ,  G11C2216/10

Abstract: A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.

Abstract translation: 非易失性存储器件包括非易失性存储器单元的网络，每个非易失性存储器单元包括浮栅晶体管，所述单元网络旨在以一组数据字的形式存储数据。 该装置包括检测存储在单元中的电荷损失的电路，然后对已检测到电荷损失的单元进行重新编程，以恢复存储电荷的电平。

公开(公告)号：US07563687B2

公开(公告)日：2009-07-21

申请号：US11302971

申请日：2005-12-14

Applicant: Jean-Christophe Giraudin ,  Sébastien Cremer ,  Philippe Delpech

Inventor： Jean-Christophe Giraudin ,  Sébastien Cremer ,  Philippe Delpech

IPC: H01L21/20

CPC classification number: H01L21/32139 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/13 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

Abstract translation: 互连层中的电容器的制造方法包括以下阶段：第一金属层（21）的沉积; 在第一金属层（21）上沉积第一绝缘体层（31）; 在第一绝缘体层（31）上沉积第二金属层（41）; 在第二层金属（41）中形成上电极（4）; 沉积覆盖上电极（4）的第二绝缘体层（13）。 蚀刻第二绝缘体层以在围绕上电极（4）的该第一绝缘体层上形成间隔物（14）; 然后通过从第一金属层和未被上电极（4）或间隔物（14）覆盖的绝缘体去除零件来形成下电极（2）和电介质（3）; 和互连线（5）的形成。 该过程允许以更低的成本和自动对准以简化的方式制造具有增加的性能的电容器。

公开(公告)号：US07536564B2

公开(公告)日：2009-05-19

申请号：US10476359

申请日：2002-04-29

Applicant: Pierre-Yvan Liardet ,  Fabrice Romain

Inventor： Pierre-Yvan Liardet ,  Fabrice Romain

IPC: H04L21/00

CPC classification number: G06F7/72 ,  G06F21/755 ,  G06F2207/7247

Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).

Abstract translation: 本发明涉及一种使用至少模块化操作（3）以随机数（r）加密计算的方法，所述方法包括将第一模（n）乘以所述随机数，以模数 操作，所述乘法的结果（m）和基于第一模（n）执行操作结果的模块化减少。

公开(公告)号：US07533412B2

公开(公告)日：2009-05-12

申请号：US10418523

申请日：2003-04-18

Applicant: Yannick Teglia

Inventor： Yannick Teglia

IPC: G06F12/14 ,  H04L9/00

CPC classification number: G06F21/52

Abstract: A method for controlling the execution of a program including of associating with each operator an initial digital code and a final digital code which are linked to each other by a degradation function applied a number of times depending on the execution of this operator; applying, to the content of a register initialized at each instruction beginning by the initial code of the corresponding operator, said degradation function a number of times depending on the operator execution; and checking, at least at each instruction end, the coherence between the register content and the final code of the corresponding operator.

Abstract translation: 一种用于控制程序的执行的方法，包括与每个操作者相关联的初始数字代码和最终的数字代码，所述初始数字代码和最终的数字代码通过根据该操作者的执行应用多次的退化功能彼此链接; 应用于由相应运算符的初始代码开始的每个指令初始化的寄存器的内容，所述退化函数根据操作者的执行次数; 并且至少在每个指令端检查寄存器内容与对应操作符的最终代码之间的一致性。

公开(公告)号：US07525390B2

公开(公告)日：2009-04-28

申请号：US11079009

申请日：2005-03-11

Applicant: Fabien Pousset ,  Jean-Charles Grasset ,  Philippe Cathelin

Inventor： Fabien Pousset ,  Jean-Charles Grasset ,  Philippe Cathelin

IPC: H03F3/04

CPC classification number: H03F3/19 ,  H03F1/0205 ,  H03F1/32 ,  H03F3/24 ,  H03F2200/06

Abstract: A circuit for converting a differential signal into a nondifferential signal comprising first and second inputs respectively receiving first and second components of a differential signal. The circuit comprises a single bipolar transistor having an emitter, a base and a collector. The transistor is biased so as to allow flowing of an emitter d.-c. bias current sufficient to allow a linear conversion of a differential RF signal, for example. Both components of the differential RF signal are respectively injected into the emitter and the base of the bipolar transistor so that a remarkably linear conversion is carried out by means of a very simple circuit. The circuit is particularly adapted to the realization of an integrated RF transmission chain.

Abstract translation: 一种用于将差分信号转换成非差分信号的电路，包括分别接收差分信号的第一和第二分量的第一和第二输入。 该电路包括具有发射极，基极和集电极的单个双极晶体管。 晶体管被偏置以允许发射极d.c.的流动。 例如，足以允许差分RF信号的线性转换的偏置电流。 差分RF信号的两个分量分别注入到双极晶体管的发射极和基极中，使得通过非常简单的电路进行显着的线性转换。 该电路特别适用于实现集成RF传输链。