公开(公告)号：US20210234546A1

公开(公告)日：2021-07-29

申请号：US17227974

申请日：2021-04-12

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Sandor PETENYI

IPC: H03L7/089 ,  H02M3/335 ,  G11C11/4074 ,  G11C5/14

Abstract: A circuit includes a current controller oscillator generating a CCO output signal at a CCO output, a charge pump boosting a supply voltage based on the CCO output signal and producing a charge pump output voltage at an output, and a current sensing circuit sensing load current at the output and generating a feedback signal having a magnitude that varies with the sensed load current if a magnitude of the sensed load current is between lower and upper load current thresholds. A frequency of the CCO output signal is constant at a lower frequency threshold where the sensed load current is below the lower load current threshold, asymptomically rises to an upper frequency threshold where the sensed load current is above the upper load current threshold, and is proportional to the feedback signal where the sensed load current is between the lower and upper load current thresholds.

公开(公告)号：US20200295767A1

公开(公告)日：2020-09-17

申请号：US16353122

申请日：2019-03-14

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Sandor PETENYI

IPC: H03L7/089 ,  G11C5/14 ,  G11C11/4074 ,  H02M3/335

Abstract: A charge pump circuit has load driven clock frequency management. The charge pump circuit includes a CCO generating a CCO output signal that has a frequency generally proportional to a feedback current, and a charge pump operated by the CCO output signal and boosting a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sensing circuit senses a load current drawn by the load and generates the feedback current as having a magnitude that varies as a function of the sensed load current if a magnitude of the load current is between a lower load current threshold and an upper load current threshold. The magnitude of the feedback current does not vary with the sensed load current if the magnitude of the sensed load current is not between the lower load current threshold and the upper load current threshold.

公开(公告)号：US20200036080A1

公开(公告)日：2020-01-30

申请号：US16521757

申请日：2019-07-25

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GmbH

Inventor： Petr OUREDNIK ,  Yvon GOURDOU

IPC: H01Q1/22 ,  H01Q1/38 ,  H01Q7/00

Abstract: An antenna includes two planar coils that are mechanically disposed face to face and electrically connected in series. The antenna is mounted to a disposable consumer product (for example, a cartridge for use with an electronic cigarette). The antenna is configured to support near field communications with a reader circuit for purposes of authenticating use of the disposable consumer product.

公开(公告)号：US10403624B2

公开(公告)日：2019-09-03

申请号：US15606773

申请日：2017-05-26

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Patrik Vacula ,  Milos Vacula ,  Miroslav Husak

IPC: H01L29/10 ,  H01L27/085 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L29/20

Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected lines that form a plurality of frames, lines of each of the frames being over the perimeter of a respective source or drain region. The shared gate includes frames of a first size and shape and frames of a second size and shape, such as squares, rectangles and octagons. The frames having the first size and shape are each over a respective source region and the frames having the second size and shape are each over a respective drain region. Each of the frames having a first size and shape share at least one side with one of the frames having the second size and shape.

公开(公告)号：US10264353B2

公开(公告)日：2019-04-16

申请号：US15473812

申请日：2017-03-30

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Alps) SAS

Inventor： Jean Claude Bini ,  Dragos Davidescu ,  Igor Cesko ,  Jonathan Cottinet

IPC: H04R3/00 ,  H04R3/04 ,  G10K11/34 ,  H04R1/40 ,  H04R19/00

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

公开(公告)号：US09823965B2

公开(公告)日：2017-11-21

申请号：US15080307

申请日：2016-03-24

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Gaetano Di Stefano ,  Antonin Fried

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1044 ,  G11C29/52

Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.

公开(公告)号：US08981746B2

公开(公告)日：2015-03-17

申请号：US13420883

申请日：2012-03-15

Applicant: Karel Napravnik

Inventor： Karel Napravnik

IPC: G05F1/40 ,  G05F1/575

CPC classification number: G05F1/575

Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.

Abstract translation: 低压差线性稳压器包括误差放大器，其包括差分放大器和增益级的级联布置。 增益级包括由差分放大器驱动的晶体管，以在调节器的输出级的驱动信号处产生。 晶体管插在其源极 - 漏极线之间，包括在RC网络中的第一电阻负载，在调节器的开环增益中产生零，并产生第二电阻负载，以产生调节器的输出级的驱动信号。 第二阻性负载是非线性补偿元件，以使电流消耗线性地与调节器的负载电流成正比。 第一阻性负载是一个非线性元件，导致RC网络产生的零点频率随着调节器负载电流的减小而减小。

公开(公告)号：US07626799B2

公开(公告)日：2009-12-01

申请号：US11832774

申请日：2007-08-02

Applicant: Tomas Jahelka ,  Jaromir Schindler

Inventor： Tomas Jahelka ,  Jaromir Schindler

IPC: H02H9/08

CPC classification number: G05F1/569 ,  G01K7/015 ,  H03F1/52 ,  H03F2200/441 ,  H03F2200/447 ,  H03F2200/468 ,  H03F2200/78

Abstract: A microelectronic device includes a first circuit and a second circuit, coupled to the first circuit for selectively preventing operation of the first circuit when a device temperature is higher than a temperature threshold. The second circuit is provided with a temperature responsive element, thermally coupled to the first circuit for providing a shutdown signal correlated to the device temperature. The temperature responsive element includes a reverse-biased junction element and the shutdown signal is correlated to a reverse leakage current of the reverse-biased junction element.

Abstract translation: 微电子器件包括耦合到第一电路的第一电路和第二电路，用于当器件温度高于温度阈值时选择性地防止第一电路的操作。 第二电路设置有热耦合到第一电路的温度响应元件，用于提供与器件温度相关的关断信号。 温度响应元件包括反向偏置接合元件，并且关断信号与反向偏压接合元件的反向泄漏电流相关。

公开(公告)号：US20090102561A1

公开(公告)日：2009-04-23

申请号：US12062576

申请日：2008-04-04

Applicant: Peter Murin ,  Hynek Saman

Inventor： Peter Murin ,  Hynek Saman

IPC: H03F1/52 ,  H03F3/26

CPC classification number: H03F3/45179 ,  H03F1/0272 ,  H03F1/342 ,  H03F1/52 ,  H03F1/526 ,  H03F3/185 ,  H03F3/3022 ,  H03F2200/03 ,  H03F2200/426 ,  H03F2200/453

Abstract: An amplifier with an output protection having an input stage defining a feedback node, an output stage connected to the feedback node and defining an output node supplying an output voltage, and a feedback stage connected between the output and the feedback nodes. A mirror stage is connected to the feedback node and has the same structure as the output stage, the mirror stage defining a reference node connected to the feedback stage for generating a reference voltage to be compared to the output voltage by the feedback stage. The feedback stage generates a current limitation signal fed to the feedback node when a difference between the output and the reference voltages is higher than a threshold.

Abstract translation: 具有输出保护的放大器具有限定反馈节点的输入级，连接到反馈节点的输出级并且定义提供输出电压的输出节点以及连接在输出和反馈节点之间的反馈级。 反射级连接到反馈节点并且具有与输出级相同的结构，镜级定义连接到反馈级的参考节点，用于产生与反馈级与输出电压进行比较的参考电压。 当输出和参考电压之间的差高于阈值时，反馈级产生馈送到反馈节点的电流限制信号。

公开(公告)号：US20080211473A1

公开(公告)日：2008-09-04

申请号：US11961401

申请日：2007-12-20

Applicant: Ondrej Tlasksl ,  Bohumil Janik ,  David Burda ,  Julien Picq ,  Miroslav Hukel

Inventor： Ondrej Tlasksl ,  Bohumil Janik ,  David Burda ,  Julien Picq ,  Miroslav Hukel

IPC: G05F1/08 ,  H02M7/02

CPC classification number: H02M1/38 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

Abstract: A synchronous rectifier, including an energy storage element having a terminal; a power supply input, connected to the terminal of the storage element in a first time interval; a reference line connected to the terminal of the storage element in a second time interval; and a zero comparator, coupled to the terminal of the storage element to detect a current flowing in the energy storage element and disconnect the terminal of the storage element from the reference line upon detecting a zero current, the zero comparator having an offset and a propagation time; the zero comparator further having an offset control input and an output. An offset regulating loop is coupled between the output of the zero comparator and the offset control input and regulates the offset of the zero comparator to compensate the propagation time.

Abstract translation: 一种同步整流器，包括具有端子的能量存储元件; 电源输入，在第一时间间隔连接到所述存储元件的终端; 在第二时间间隔连接到所述存储元件的终端的参考线; 以及零比较器，耦合到存储元件的端子以检测流过能量存储元件的电流，并且在检测到零电流时将存储元件的端子与参考线断开，零比较器具有偏移和传播 时间; 该零比较器还具有偏移控制输入和输出。 偏移调节回路耦合在零比较器的输出和偏移控制输入之间，并调节零比较器的偏移量以补偿传播时间。