公开(公告)号：US12169430B2

公开(公告)日：2024-12-17

申请号：US17824844

申请日：2022-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Raul Gutierrez

IPC: G06F1/3234 ,  G06F13/10

Abstract: Systems and methods are disclosed for reducing power consumed by capturing data from an I/O device. Techniques disclosed include receiving descriptors, by a controller of an I/O host of a system, including information associated with respective data chunks to be captured from an I/O device buffer of the I/O device. Techniques disclosed further include capturing, based on the descriptors, the data chunks. The capturing comprises pulling the data chunks from the I/O device buffer at a pulling rate, where the data chunks are transferred to a local buffer of the I/O host, and pushing segments of the pulled data chunks from the local buffer, where each segment is transferred to a data buffer of the system after a respective target time that precedes a time at which the data chunks in the segment are to be processed by an application executing on the system.

公开(公告)号：US20240412445A1

公开(公告)日：2024-12-12

申请号：US18332562

申请日：2023-06-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： David William John Pankratz ,  David Ronald Oldcorn

IPC: G06T15/06 ,  G06T15/00

Abstract: A technique for performing ray tracing operations is provided. The technique includes, traversing through a bounding volume hierarchy for a ray to arrive at a well-fit bounding volume that is associated with first node, wherein the first node is one of a traversal node or a procedural node, and wherein the well-fit bounding volume comprises geometry other than a single axis-aligned bounding box for the first node; evaluating the ray for intersection with the well-fit bounding volume; determining whether to execute a first shader program associated with the first node based on the evaluating, wherein the first shader program comprises a traversal shader program or a procedural shader program; and executing or not executing the first shader program based on the determining.

公开(公告)号：US20240411692A1

公开(公告)日：2024-12-12

申请号：US18332112

申请日：2023-06-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Hsiuwei Loh ,  Joseph Lee Greathouse ,  William Louie Walker ,  Paul James Moyer

IPC: G06F12/0802

Abstract: Cache replacement policies are described. In accordance with the described techniques, a request for data is received and a cache replacement policy controls how a controller responds to the request. The cache replacement policy assigns each cacheline a priority value, which indicates whether the cacheline should be preserved relative to other cachelines, in response to the request being a cache miss that necessitates eviction of at least one cacheline. The cache replacement policy decrements priority values until at least one cacheline achieves a minimum priority value, at which point a cacheline is evicted. The cache replacement policy designates certain cachelines as protected, either via a separate protected indicator or via the cacheline's priority value, which causes unprotected cachelines to be selected for eviction while favoring preservation of protected cachelines in the cache.

公开(公告)号：US12165700B2

公开(公告)日：2024-12-10

申请号：US17488519

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu ,  Keith A. Kasprak

IPC: G11C11/419 ,  G11C11/418

Abstract: A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

公开(公告)号：US12165252B2

公开(公告)日：2024-12-10

申请号：US18480466

申请日：2023-10-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind N. Nemlekar ,  Maxim V. Kazakov ,  Prerit Dak

IPC: G06T15/00 ,  G06F9/54 ,  G06T15/80

Abstract: Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such completion and proceeding to a subsequent kernel dispatch packet.

公开(公告)号：US12164353B2

公开(公告)日：2024-12-10

申请号：US17936740

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Shang Yang

IPC: G06F1/3206

Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

公开(公告)号：US20240406416A1

公开(公告)日：2024-12-05

申请号：US18206056

申请日：2023-06-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Thompson ,  Jonathan Philip Bonsor-Matthews

IPC: H04N19/172

Abstract: A processing unit (PU) is configured to generate reference values based on previously displayed frames in order to decode encoded frames having one or more noise-based effects. To this end, the PU includes a noise effect circuitry configured to determine noise values associated with a previously displayed frame. The noise effect circuitry then subtracts respective noise values from the pixel values of the previously displayed frame to determine reference values for decoding an encoded frame. Further, the PU includes a decoder that decodes the encoded frame based on the determined reference values.

公开(公告)号：US20240404897A1

公开(公告)日：2024-12-05

申请号：US18676665

申请日：2024-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Mihir PANDYA ,  Liwei WANG ,  Samuel NAFFZIGER

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

Abstract: A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.

公开(公告)号：US20240403121A1

公开(公告)日：2024-12-05

申请号：US18203360

申请日：2023-05-30

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Anil Harwani ,  Paul Blinzer ,  Kenneth Lawrence Mitchell ,  Adam Neil Calder Clark ,  Amitabh Mehra ,  Joshua Taylor Knight ,  Grant Evan Ley ,  Jerry Anton Ahrens ,  William Robert Alverson

IPC: G06F9/50

Abstract: Task scheduling based on component margins is described. In accordance with the described techniques, a scheduler of an operating system accesses a margin table when a request to perform tasks is received. The scheduler schedules tasks on various components of a system based on margins of those components. When a request to perform a task is received, for example, the scheduler accesses the margin table and selects a component to perform the task based on the margin information included in the margin table as well as based on the task, such as whether the task benefits more from being performed fast or being performed accurately. The scheduler then schedules the task using the selected component.

公开(公告)号：US12158842B2

公开(公告)日：2024-12-03

申请号：US17956995

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Youngjae Cho ,  Armand Bahram Behroozi ,  Michael L. Chu ,  Ashwin Aji

IPC: G06F12/02 ,  G06F12/06

Abstract: A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.