公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

Applicant: Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

Inventor： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract translation: 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US20090081837A1

公开(公告)日：2009-03-26

申请号：US11861492

申请日：2007-09-26

Applicant: Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

Inventor： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract translation: 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US06365516B1

公开(公告)日：2002-04-02

申请号：US09483081

申请日：2000-01-14

Applicant: Austin Frenkel ,  Akif Sultan ,  Paul Besser

Inventor： Austin Frenkel ,  Akif Sultan ,  Paul Besser

IPC: H01L2144

CPC classification number: H01L21/0206 ,  H01L21/28518

Abstract: Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.

Abstract translation: 提供了制造硅化物结构的各种方法。 一方面，提供一种在硅表面上制造电路结构的方法，其包括将硅表面暴露于含有氢气和惰性气体的等离子体环境中，以及在硅表面上沉积能够形成硅化物的金属材料。 金属材料被加热以在硅表面上形成金属硅化物。 该方法通过消除天然氧化物膜而不会产生间隔材料反溅镀的风险，从而提供低电阻硅化物结构。

公开(公告)号：US06346463B1

公开(公告)日：2002-02-12

申请号：US09565858

申请日：2000-05-05

Applicant: Akif Sultan ,  Frederick N. Hause

Inventor： Akif Sultan ,  Frederick N. Hause

IPC: H01L2104

CPC classification number: H01L29/1079 ,  H01L21/26513 ,  H01L21/823493

Abstract: A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above the first epitaxial layer. The second concentration is greater than the first concentration. A third epitaxial layer having a third dopant at a third concentration is formed above the second epitaxial layer. The third concentration is less than the second concentration. Ions are implanted in the third epitaxial layer to form an implant region. The implant region is in contact with the second epitaxial layer. A semiconductor device comprises a base layer, first, second, and third epitaxial layers, and an implant region. The first epitaxial layer has a first dopant at a first concentration disposed above the base layer. The second epitaxial layer has a second dopant at a second concentration disposed above the first epitaxial layer. The second concentration is greater than the first concentration. The third epitaxial layer has a third dopant at a third concentration disposed above the second epitaxial layer. The third concentration is less than the second concentration. The implant region is defined in the third epitaxial layer and is in contact with the second epitaxial layer.

Abstract translation: 提供一种形成半导体器件的方法。 提供基层。 具有第一浓度的第一掺杂剂的第一外延层形成在基层之上。 具有第二浓度的第二掺杂剂的第二外延层形成在第一外延层的上方。 第二浓度大于第一浓度。 具有第三浓度的第三掺杂剂的第三外延层形成在第二外延层的上方。 第三浓度小于第二浓度。 将离子注入第三外延层以形成植入区。 注入区域与第二外延层接触。 半导体器件包括基极层，第一，第二和第三外延层以及植入区域。 第一外延层具有设置在基极层之上的第一浓度的第一掺杂剂。 第二外延层具有设置在第一外延层上方的第二浓度的第二掺杂剂。 第二浓度大于第一浓度。 第三外延层具有设置在第二外延层上方的第三浓度的第三掺杂剂。 第三浓度小于第二浓度。 注入区域限定在第三外延层中并且与第二外延层接触。

公开(公告)号：US6063682A

公开(公告)日：2000-05-16

申请号：US49322

申请日：1998-03-27

Applicant: Akif Sultan ,  Geoffrey Choh-Fei Yeap

Inventor： Akif Sultan ,  Geoffrey Choh-Fei Yeap

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2652 ,  Y10S438/918

Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract translation: 提供一种制造晶体管的方法。 根据该方法，将重离子注入到硅衬底中，以使至少一部分硅衬底非晶化。 非晶化硅基本上不含通道。 随后将掺杂剂注入到非晶化硅中，并且非晶化硅基本上包含注入的掺杂剂。 此后，进行硅注入步骤以在预定范围内产生过多的间隙空隙。 由于在该预定范围内间隙的空位过多，掺杂剂在预定范围内的增强扩散减轻。