公开(公告)号：US20080297217A1

公开(公告)日：2008-12-04

申请号：US11930596

申请日：2007-10-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03L7/06

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US20070200539A1

公开(公告)日：2007-08-30

申请号：US11362982

申请日：2006-02-27

Applicant: Ramkishore Ganti ,  Caiyi Wang ,  Augusto Marques

Inventor： Ramkishore Ganti ,  Caiyi Wang ,  Augusto Marques

IPC: G05F1/00

CPC classification number: G05F1/56 ,  H02M3/155 ,  H02M2001/0045

Abstract: An apparatus comprises a circuit having a power supply node and a linear regulator configured to provide a regulated voltage at the power supply node of the circuit. The apparatus further comprises a switching regulator configured to provide input power to the linear regulator from a power source such as a battery. In some implementations, the circuit is a transceiver circuit.

Abstract translation: 一种装置包括具有电源节点的电路和被配置为在电路的电源节点处提供调节电压的线性调节器。 该装置还包括开关调节器，其被配置为从诸如电池的电源向线性调节器提供输入功率。 在一些实现中，电路是收发器电路。

公开(公告)号：US07221921B2

公开(公告)日：2007-05-22

申请号：US10730404

申请日：2003-12-08

Applicant: James Maligeorgos ,  Augusto M. Marques ,  Lysander Lim ,  G. Tyson Tuttle ,  Aslamali A. Rafi ,  Tod Paulus ,  Gregory T. Uehara ,  Jeffrey W. Scott ,  Richard T. Behrens ,  Donald A. Kerth ,  G. Diwakar Vishakhadatta ,  Vishnu S. Srinivasan ,  Caiyi Wang

Inventor： James Maligeorgos ,  Augusto M. Marques ,  Lysander Lim ,  G. Tyson Tuttle ,  Aslamali A. Rafi ,  Tod Paulus ,  Gregory T. Uehara ,  Jeffrey W. Scott ,  Richard T. Behrens ,  Donald A. Kerth ,  G. Diwakar Vishakhadatta ,  Vishnu S. Srinivasan ,  Caiyi Wang

IPC: H04B7/00 ,  H04B1/40 ,  H03J7/04

CPC classification number: H04B1/30 ,  H03J2200/10 ,  H04L27/0002

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

公开(公告)号：US07199650B1

公开(公告)日：2007-04-03

申请号：US11169416

申请日：2005-06-29

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US20060073793A1

公开(公告)日：2006-04-06

申请号：US11224391

申请日：2005-09-12

Applicant: David Welland ,  Ramkishore Ganti ,  CaiYi Wang

Inventor： David Welland ,  Ramkishore Ganti ,  CaiYi Wang

IPC: H04B1/40 ,  H04B1/06

CPC classification number: H04B1/403

Abstract: An RF transmitter (104) includes a shared local oscillator circuit (126), transmit path circuitry (120, 122, 124), a divider (134), and a lowpass filter (322). The shared local oscillator circuit (126) generates a shared LO signal (116). The transmit path circuitry (120, 122, 124) mixes a baseband signal (107) and an IF mixing signal (116) to provide an IF signal (112), and converts the IF signal (112) to an RF transmit signal (105) at a desired frequency using an RF mixing signal received at a mixing input thereof. The divider (134) divides the shared LO signal (116) to provide an unfiltered RF mixing signal. The lowpass filter (322) has an input for receiving the unfiltered RF mixing signal, and an output coupled to the mixing input of the transmit path circuitry (120, 122, 124) for providing the RF mixing signal.

Abstract translation: RF发射机（104）包括共享本地振荡器电路（126），发射路径电路（120,122,124），分频器（134）和低通滤波器（322）。 共享本地振荡器电路（126）产生共享LO信号（116）。 发射路径电路（120,122,124）混合基带信号（107）和IF混合信号（116）以提供IF信号（112），并将IF信号（112）转换成RF发射信号（105 ），使用在其混合输入端接收的RF混频信号。 分频器（134）划分共享LO信号（116）以提供未滤波的RF混频信号。 低通滤波器（322）具有用于接收未滤波的RF混频信号的输入端和耦合到发射路径电路（120,122,124）的混频输入的输出，用于提供RF混频信号。

公开(公告)号：US06993307B2

公开(公告)日：2006-01-31

申请号：US10681405

申请日：2003-10-08

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B7/00

CPC classification number: H03L7/099 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

公开(公告)号：US20060003707A1

公开(公告)日：2006-01-05

申请号：US11096134

申请日：2005-03-31

Applicant: David Welland ,  Caiyi Wang

Inventor： David Welland ,  Caiyi Wang

IPC: H04B1/40 ,  H04B1/02 ,  H01Q11/12 ,  H04B1/66

CPC classification number: H04B1/403

Abstract: Mixing circuitry for quadrature processing in communication systems and related methods are disclosed. The weighted mixing circuitry allows for arbitrary dividers to be utilized in generating the mixing signals for quadrature processing and thereby provides a significant advantage over prior architectures where 90 degree offset I and Q mixing signals were needed for quadrature mixing.

Abstract translation: 公开了用于通信系统中的正交处理的混合电路及相关方法。 加权混合电路允许任意的分频器用于生成用于正交处理的混合信号，并且因此提供了相对于其中需要90度偏移I和Q混合信号以进行正交混合的现有架构的显着优点。

公开(公告)号：US06750906B1

公开(公告)日：2004-06-15

申请号：US09075446

申请日：1998-05-08

Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC: H04N5235

CPC classification number: H04N5/2352

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US06317006B1

公开(公告)日：2001-11-13

申请号：US09621803

申请日：2000-07-21

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H03B508

CPC classification number: H03L7/099 ,  H03D7/163 ,  H03J2200/10 ,  H03L7/087 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23 ,  H04B1/26 ,  H04B1/30

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register. The shift register may be clocked by another clock signal at a higher frequency than the divided version of the VCO output clock. The phase differences between the plurality of phase shifted signals and a divided version of a reference clock may then be detected and converted to the analog control signals.

Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过使用移位寄存器首先从VCO输出时钟的分割版本生成多个相移信号来导出模拟控制信号。 移位寄存器可以以比VCO输出时钟的分频版本更高的频率由另一个时钟信号来计时。 然后可以检测多个相移信号和参考时钟的分割版本之间的相位差并转换成模拟控制信号。

公开(公告)号：US06308055B1

公开(公告)日：2001-10-23

申请号：US09087486

申请日：1998-05-29

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04Q720

CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。