公开(公告)号：US20060003706A1

公开(公告)日：2006-01-05

申请号：US11096133

申请日：2005-03-31

Applicant: David Welland ,  Caiyi Wang

Inventor： David Welland ,  Caiyi Wang

IPC: H04B1/40 ,  H04B1/02 ,  H01Q11/12 ,  H04B1/66

CPC classification number: H04B1/403

Abstract: A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.

Abstract translation: 公开了用于通信系统和相关方法的比例传输路径架构。 这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要 以前的解决方案。

公开(公告)号：US20060197847A1

公开(公告)日：2006-09-07

申请号：US11415000

申请日：2006-05-01

Applicant: Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

Inventor： Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

IPC: H04N5/235

CPC classification number: H04N5/3575 ,  H04N5/335 ,  H04N5/361

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

公开(公告)号：US20060073793A1

公开(公告)日：2006-04-06

申请号：US11224391

申请日：2005-09-12

Applicant: David Welland ,  Ramkishore Ganti ,  CaiYi Wang

Inventor： David Welland ,  Ramkishore Ganti ,  CaiYi Wang

IPC: H04B1/40 ,  H04B1/06

CPC classification number: H04B1/403

Abstract: An RF transmitter (104) includes a shared local oscillator circuit (126), transmit path circuitry (120, 122, 124), a divider (134), and a lowpass filter (322). The shared local oscillator circuit (126) generates a shared LO signal (116). The transmit path circuitry (120, 122, 124) mixes a baseband signal (107) and an IF mixing signal (116) to provide an IF signal (112), and converts the IF signal (112) to an RF transmit signal (105) at a desired frequency using an RF mixing signal received at a mixing input thereof. The divider (134) divides the shared LO signal (116) to provide an unfiltered RF mixing signal. The lowpass filter (322) has an input for receiving the unfiltered RF mixing signal, and an output coupled to the mixing input of the transmit path circuitry (120, 122, 124) for providing the RF mixing signal.

Abstract translation: RF发射机（104）包括共享本地振荡器电路（126），发射路径电路（120,122,124），分频器（134）和低通滤波器（322）。 共享本地振荡器电路（126）产生共享LO信号（116）。 发射路径电路（120,122,124）混合基带信号（107）和IF混合信号（116）以提供IF信号（112），并将IF信号（112）转换成RF发射信号（105 ），使用在其混合输入端接收的RF混频信号。 分频器（134）划分共享LO信号（116）以提供未滤波的RF混频信号。 低通滤波器（322）具有用于接收未滤波的RF混频信号的输入端和耦合到发射路径电路（120,122,124）的混频输入的输出，用于提供RF混频信号。

公开(公告)号：US20060003707A1

公开(公告)日：2006-01-05

申请号：US11096134

申请日：2005-03-31

Applicant: David Welland ,  Caiyi Wang

Inventor： David Welland ,  Caiyi Wang

IPC: H04B1/40 ,  H04B1/02 ,  H01Q11/12 ,  H04B1/66

CPC classification number: H04B1/403

Abstract: Mixing circuitry for quadrature processing in communication systems and related methods are disclosed. The weighted mixing circuitry allows for arbitrary dividers to be utilized in generating the mixing signals for quadrature processing and thereby provides a significant advantage over prior architectures where 90 degree offset I and Q mixing signals were needed for quadrature mixing.

Abstract translation: 公开了用于通信系统中的正交处理的混合电路及相关方法。 加权混合电路允许任意的分频器用于生成用于正交处理的混合信号，并且因此提供了相对于其中需要90度偏移I和Q混合信号以进行正交混合的现有架构的显着优点。

公开(公告)号：US20050266817A1

公开(公告)日：2005-12-01

申请号：US11180267

申请日：2005-07-13

Applicant: David Welland ,  Caiyi Wang

Inventor： David Welland ,  Caiyi Wang

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/193 ,  H03L7/199 ,  H03L7/23 ,  H04B1/06 ,  H04B1/40 ,  H04B7/00

CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

公开(公告)号：US20050024509A1

公开(公告)日：2005-02-03

申请号：US10862488

申请日：2004-06-07

Applicant: Nadi Itani ,  Caiyi Wang ,  David Welland

Inventor： Nadi Itani ,  Caiyi Wang ,  David Welland

IPC: G06T5/40 ,  H04N5/235 ,  H04N5/243 ,  H04N5/351 ,  H04N5/378 ,  H04N5/20

CPC classification number: H04N5/2352

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US20070072558A1

公开(公告)日：2007-03-29

申请号：US11394249

申请日：2006-03-30

Applicant: Srinath Sridharan ,  Ahmed Emira ,  Aria Eshraghi ,  David Welland

Inventor： Srinath Sridharan ,  Ahmed Emira ,  Aria Eshraghi ,  David Welland

IPC: H01Q11/12 ,  H04B1/04

CPC classification number: H04B1/0475

Abstract: A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.

Abstract translation: 一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。 使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。

公开(公告)号：US20060215771A1

公开(公告)日：2006-09-28

申请号：US11398090

申请日：2006-04-05

Applicant: Jeffrey Scott ,  Navdeep Sooch ,  David Welland

Inventor： Jeffrey Scott ,  Navdeep Sooch ,  David Welland

IPC: H04L25/00

CPC classification number: H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

公开(公告)号：US20080008259A1

公开(公告)日：2008-01-10

申请号：US11900957

申请日：2007-09-14

Applicant: G. Tuttle ,  David Welland ,  Scott Willingham

Inventor： G. Tuttle ,  David Welland ,  Scott Willingham

IPC: H04L7/027

CPC classification number: H04B1/30

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract translation: 公开了一种用于集成接收机和相关方法的比例时钟系统，其提供用于将数字信号处理（DSP）电路组合在与混频器和本地振荡器（LO）生成电路相同的集成电路上的有利解决方案。 产生电路产生振荡信号，该信号通过第一分频器以产生用于混频器的混频信号，并通过第二分频器产生由DSP电路利用的数字时钟信号。 该数字时钟信号也可以由集成的模数转换电路使用。

公开(公告)号：US20070071129A1

公开(公告)日：2007-03-29

申请号：US11510339

申请日：2006-08-25

Applicant: David Welland

Inventor： David Welland

IPC: H04L27/20

CPC classification number: H04L27/0008 ,  H04B1/04

Abstract: In one embodiment, the present invention includes an apparatus having multiple transmission paths, including a first transmission path configured to receive and process baseband data in a first mode of operation to generate a radio frequency (RF) signal for output via a common output path, and a second transmission path configured to receive and process the baseband data in a second mode of operation to generate the RF signal for output via the common output path.

Abstract translation: 在一个实施例中，本发明包括具有多个传输路径的设备，包括：第一传输路径，其被配置为在第一操作模式中接收和处理基带数据，以产生用于经由公共输出路径输出的射频（RF）信号; 以及第二传输路径，其被配置为在第二操作模式中接收和处理所述基带数据，以产生所述RF信号以经由所述公共输出路径输出。