中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

121 records (took 0.015 seconds)

    CMOS DEVICE AND METHOD OF MANUFACTURING THE SAME
    41.
    发明申请
    CMOS DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    CMOS器件及其制造方法

    公开(公告)号：US20080157141A1

    公开(公告)日：2008-07-03

    申请号：US11875419

    申请日：2007-10-19

    Applicant: Chang Hun Han

    Inventor： Chang Hun Han

    IPC: H01L31/113 ,  H01L27/146 ,  H01L31/18

    CPC classification number: H01L27/14692 ,  H01L23/38 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/16 ,  H01L31/024 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a CMOS device including: sequentially forming a first silicon oxide film and a first polysilicon film on a lower substrate; performing an ion implantation process with respect to the first polysilicon film to form a plurality of lower conductors spaced apart from one another at a predetermined interval; forming a plurality of N-type semiconductor films and P-type semiconductor films which are formed by being spaced apart from one another at a predetermined interval and are in contact with the lower conductors; forming a plurality of upper conductors electrically connected to the N-type semiconductor films and P-type semiconductor films; forming an upper substrate on the upper conductors; forming a second polysilicon film on the upper substrate; forming a device isolation film and a photodiode in the second polysilicon film; forming a gate electrode including an insulating sidewall on the second polysilicon film; forming an insulating film on an epitaxial layer with the gate electrode; forming a color filter array on the insulating film; forming a planarization layer on the color filter array; and forming a microlens on the planarization layer.

    Abstract translation: 一种制造CMOS器件的方法，包括：在下基板上依次形成第一氧化硅膜和第一多晶硅膜; 对所述第一多晶硅膜进行离子注入工艺以形成以预定间隔彼此间隔开的多个下导体; 形成多个N型半导体膜和P型半导体膜，它们以预定间隔彼此间隔开并与下导体接触; 形成电连接到N型半导体膜和P型半导体膜的多个上导体; 在上导体上形成上基板; 在上基板上形成第二多晶硅膜; 在所述第二多晶硅膜中形成器件隔离膜和光电二极管; 在所述第二多晶硅膜上形成包括绝缘侧壁的栅电极; 在栅电极的外延层上形成绝缘膜; 在绝缘膜上形成滤色器阵列; 在所述滤色器阵列上形成平坦化层; 并在平坦化层上形成微透镜。

    Methods of fabricating semiconductor devices
    43.
    发明授权
    Methods of fabricating semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US07135371B2

    公开(公告)日：2006-11-14

    申请号：US10747602

    申请日：2003-12-29

    Applicant: Chang Hun Han ,  Dong Yeal Keum

    Inventor： Chang Hun Han ,  Dong Yeal Keum

    IPC: H01L21/336

    CPC classification number: H01L21/823475 ,  H01L21/76232 ,  H01L21/823481

    Abstract: Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in the substrate; forming spacers on the sidewalls of the gate electrode; performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as mask; forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers; forming a sidewall oxide layer on the resulting substrate; forming a diffusion barrier on the sidewall oxide layer; depositing a gap filling insulation layer over the diffusion barrier; planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

    Abstract translation: 公开了制造半导体器件的方法。 一种示例性方法包括在半导体衬底上形成栅极氧化物和栅电极; 执行用于在衬底中形成LDD（轻掺杂漏极）区域的第一离子注入工艺; 在栅电极的侧壁上形成间隔物; 执行第二离子注入工艺，以使用间隔物作为掩模在衬底中形成接合区域; 通过选择性地去除所述间隔物之间​​的所述衬底的顶部而形成用于器件隔离的沟槽; 在所得衬底上形成侧壁氧化物层; 在侧壁氧化物层上形成扩散阻挡层; 在扩散阻挡层上沉积间隙填充绝缘层; 平面化间隙填充绝缘层; 并且选择性地移除间隙填充绝缘层的一部分以形成接触孔。

    Method for preparing styrenic resin having high impact strength and gloss
    44.
    发明授权
    Method for preparing styrenic resin having high impact strength and gloss 有权

    公开(公告)号：US07132474B2

    公开(公告)日：2006-11-07

    申请号：US11222164

    申请日：2005-09-08

    Applicant: Jae-burn Seo ,  Sang-seop Kim ,  Chang-hun Han

    Inventor： Jae-burn Seo ,  Sang-seop Kim ,  Chang-hun Han

    IPC: C08F297/04

    CPC classification number: C08F279/04 ,  C08L55/02 ,  Y10S525/942 ,  C08L2666/02

    Abstract: The present invention relates to a preparation method for acrylonitrile-butadiene-styrene resin by continuous bulk polymerization comprising the following steps of a) preparing a mixed solution of styrene monomers and acrylonitrile monomers by adding 5–10 weight % of the mixture of styrene monomers and acrylonitrile monomers to a reaction solvent; b) preparing a polymerization solution by dissolving butadiene rubber in the above mixed solution of styrene monomers and acrylonitrile monomers; c) polymerizing with a serial injection of the prepared polymerization solution and initiator in a grafting reactor; d) polymerizing the reaction solution of the above c) in a phase inversion reactor by adding 90–95 weight % of the total mixture of styrene monomers and acrylonitrile monomers thereto; and e) polymerizing further the reaction solution of the above step d) at 130–160° C. The resin prepared by the method of the present invention thus has excellent impact strength and gloss.

    Method of manufacturing a flash memory device
    45.
    发明申请
    Method of manufacturing a flash memory device 审中-公开
    制造闪存装置的方法

    公开(公告)号：US20060148175A1

    公开(公告)日：2006-07-06

    申请号：US11320586

    申请日：2005-12-30

    Applicant: Dong-Oog Kim ,  Chang-Hun Han

    Inventor： Dong-Oog Kim ,  Chang-Hun Han

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: A method of manufacturing a semiconductor device includes forming a polysilicon layer on a trench isolation layer and a tunnel oxide layer formed on a semiconductor substrate, and doping the polysilicon layer with germanium or argon. The doped polysilicon layer is patterned to form a floating gate electrode layer pattern. A charge-trapping layer is formed on the floating gate electrode layer pattern, and a control gate electrode layer pattern is formed on the charge-trapping layer.

    Abstract translation: 制造半导体器件的方法包括在沟槽隔离层上形成多晶硅层，在半导体衬底上形成隧道氧化物层，并用锗或氩掺杂多晶硅层。 图案化掺杂多晶硅层以形成浮栅电极层图案。 在浮栅电极层图案上形成电荷捕获层，并且在电荷捕获层上形成控制栅电极层图案。

Patent Agency Ranking