公开(公告)号：US07501333B2

公开(公告)日：2009-03-10

申请号：US11458503

申请日：2006-07-19

Applicant: Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/517

Abstract: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

Abstract translation: 具有可选工作功能的完全硅化栅包括： 衬底上的栅极电介质; 以及在所述栅极电介质上的第一金属硅化物层，以及第二金属硅化物层，其中所述第一金属硅化物具有与所述第二金属硅化物层不同的相。 金属硅化物层包括至少一种合金元素。 栅极电介质和金属硅化物层之间的界面上的合金元素的浓度影响栅极的功函数。

公开(公告)号：US20080290416A1

公开(公告)日：2008-11-27

申请号：US11751403

申请日：2007-05-21

Applicant: Chen-Hua Yu ,  Liang-Gi Yao ,  Cheng-Tung Lin

Inventor： Chen-Hua Yu ,  Liang-Gi Yao ,  Cheng-Tung Lin

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/26566 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/518

Abstract: A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material having an increased work function of about 4.7 or 4.8 eV or greater. A TaC film may be converted to a material of TaCO, TaCN, or TaCON using this technique. The layer of material including original N-metal portions and converted P-metal portions is then patterned using a single patterning operation to simultaneously form semiconductor devices from both the unconverted N-metal sections and converted P-metal sections.

Abstract translation: 在高k电介质层上形成功函数约4.3或4.4eV或更小的P金属材料层。 通过引入添加剂如O，C，N，Si等将N金属层的一部分转化为P金属材料，以产生具有约4.7或4.8eV或更大功函数的P金属材料。 使用这种技术可以将TaC膜转变为TaCO，TaCN或TaCON的材料。 然后使用单一图案化操作来构图包括原始N-金属部分和转换的P金属部分的材料层，以同时从未转换的N金属部分和转换的P金属部分形成半导体器件。

公开(公告)号：US07446042B2

公开(公告)日：2008-11-04

申请号：US11343648

申请日：2006-01-30

Applicant: Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than the temperature required for the formation of nickel silicide. Nickel diffusion is minimized during the deposition process. After deposition, an annealing process is used to urge the formation of a uniform silicide film. In various embodiments, the metal film may include a binary phase alloy containing nickel and a further element.

Abstract translation: 一种形成硅化镍的方法包括对包含硅表面的半导体衬底脱气。 在脱气操作之后，在金属沉积工艺，金属沉积工艺期间或两者之间冷却基板。 冷却将基板的温度抑制到低于形成硅化镍所需的温度的温度。 在沉积过程中镍的扩散最小化。 沉积后，使用退火工艺来促使形成均匀的硅化物膜。 在各种实施例中，金属膜可以包括含有镍和另一元素的二元相合金。

公开(公告)号：US07396767B2

公开(公告)日：2008-07-08

申请号：US10892915

申请日：2004-07-16

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

Abstract: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Abstract translation: 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

公开(公告)号：US20060011996A1

公开(公告)日：2006-01-19

申请号：US10892915

申请日：2004-07-16

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

Abstract: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Abstract translation: 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

公开(公告)号：USD482930S1

公开(公告)日：2003-12-02

申请号：US29177175

申请日：2003-03-06

Applicant: Cheng Tung Lin

Designer： Cheng Tung Lin

公开(公告)号：US06365325B1

公开(公告)日：2002-04-02

申请号：US09247791

申请日：1999-02-10

Applicant: Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

Inventor： Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

IPC: G03C500

CPC classification number: G03F7/40

Abstract: A method for fabricating a microelectronic layer. There is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture, where the first aperture has a first aperture width which exposes a first portion of the target layer. There is then reflowed thermally the patterned photoresist layer to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture. The second aperture has a second aperture width less than the first aperture width, and the second aperture thus exposes a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer. Finally, there is then fabricated the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer. The method is useful insofar as it allows the target layer to be fabricated while avoiding the use of advanced microelectronic fabrication photolithographic tooling when forming the patterned photoresist layer.

Abstract translation: 一种制造微电子层的方法。 首先提供基板。 然后在衬底上形成靶层。 然后在目标层上形成限定第一孔的图案化光致抗蚀剂层，其中第一孔具有暴露目标层的第一部分的第一孔宽度。 然后将图案化的光致抗蚀剂层热回流以形成限定基本上直的第二孔的回流图案化光致抗蚀剂层。 第二孔径具有小于第一孔径宽度的第二孔径宽度，并且第二孔口因此暴露了覆盖层目标层的面积尺寸小于覆盖层目标层的第一部分的第二部分。 最后，然后制造目标层以形成制造的目标层，同时使用回流图案化的光致抗蚀剂层作为掩模层。 该方法是有用的，只要它允许制造目标层，同时避免在形成图案化的光致抗蚀剂层时使用先进的微电子制造光刻工具。

公开(公告)号：US5536676A

公开(公告)日：1996-07-16

申请号：US415666

申请日：1995-04-03

Applicant: Huang-Chung Cheng ,  Cheng-Tung Lin ,  Chi-Hung Chao

Inventor： Huang-Chung Cheng ,  Cheng-Tung Lin ,  Chi-Hung Chao

IPC: H01L21/225 ,  H01L21/285 ,  H01L21/283

CPC classification number: H01L21/2257 ,  H01L21/28518

Abstract: A method for forming silicided shallow junctions, wherein impurities are implanted into a silicon layer formed over a silicon substrate. A metal layer selected from one of platinum (Pt), palladium (Pd), nickel (Ni) and cobalt (Co) is deposited over the silicon layer. At least one low temperature annealing process is carried out to form a silicide layer as well as the shallow junctions. Pre-anneal of the silicon layer and post-anneal of the silicide between 450.degree. and 600.degree. C. are also employed.

Abstract translation: 一种形成硅化浅结的方法，其中将杂质注入形成在硅衬底上的硅层中。 选自铂（Pt），钯（Pd），镍（Ni）和钴（Co）中的一种的金属层沉积在硅层上。 进行至少一个低温退火处理以形成硅化物层以及浅结。 还采用硅层的预退火和450℃至600℃之间的硅化物退火。